On Wed, Jul 27, 2016 at 05:35:09AM +0000, Rich Felker wrote: > Signed-off-by: Rich Felker <dal...@libc.org> > --- > .../bindings/interrupt-controller/jcore,aic.txt | 26 > ++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > > diff --git > a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > new file mode 100644 > index 0000000..b7a56ad > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt > @@ -0,0 +1,26 @@ > +J-Core Advanced Interrupt Controller > + > +Required properties: > + > +- compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic > + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for > + the "aic2" core with 64 interrupts. > + > +- reg: Memory region(s) for configuration. For SMP, there should be one > + region per cpu, indexed by the sequential, zero-based hardware cpu > + number (which is also the logical cpu number).
Nit: remove the bit about the logical number. That's a linux detail that doesn't belong in the binding. > +- interrupt-controller: Identifies the node as an interrupt controller > + > +- #interrupt-cells: Specifies the number of cells needed to encode an > + interrupt source. The value shall be 1. ... where the value encoded in that cell is? I guess it's the zero-based index of the interrupt? No flags? Can the AIC only do one trigger type? Thanks, Mark.
