Hi,
On some ARM platform with multiple pci bridges, I had to add the below
patch in order to enable transactions through the bridges to devices
behind. I'm sure there are other platforms with similar pci setup so
why wouldn't it work without it?
Thanks,
Bahadir
Enable bus transactions behind bridges.
From: Bahadir Balban <[EMAIL PROTECTED]>
When transactions (MEM/IO) are enabled for a device, this patch ensures
also the same transactions are enabled for the bridge that they sit behind.
---
drivers/pci/setup-bus.c | 17 +++++++++++++++++
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 8f7bcf5..a5c400e 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -150,0 +151 @@ EXPORT_SYMBOL(pci_setup_cardbus);
+ int i;
@@ -158,0 +160 @@ pci_setup_bridge(struct pci_bus *bus)
+ int i;
@@ -224,0 +227,15 @@ pci_setup_bridge(struct pci_bus *bus)
+
+ for (i = 0; i < 3; i++) {
+ u16 csr;
+ if ((bus->resource[i]->flags & IORESOURCE_MEM) ||
+ (bus->resource[i]->flags & IORESOURCE_PREFETCH)) {
+ pci_read_config_word(bridge, PCI_COMMAND, &csr);
+ csr |= (1 << 1) | (1 << 2);
+ pci_write_config_word(bridge, PCI_COMMAND, csr);
+ }
+ if (bus->resource[i]->flags & IORESOURCE_IO) {
+ pci_read_config_word(bridge, PCI_COMMAND, &csr);
+ csr |= (1 << 0) | (1 << 2);
+ pci_write_config_word(bridge, PCI_COMMAND, csr);
+ }
+ }
-
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