On 19/04/16 10:43, Laxman Dewangan wrote: > NVIDIA's Tegra210 support the HW debounce in the GPIO > controller for all its GPIO pins. > > Add support for setting debounce timing by implementing the > set_debounce callback of gpiochip. > > Signed-off-by: Laxman Dewangan <ldewan...@nvidia.com> > > --- > Changes from V1: > - Write debounce count before enable. > - Make sure the debounce count do not have any boot residuals. > --- > drivers/gpio/gpio-tegra.c | 49 > +++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 49 insertions(+)
[snip] > @@ -327,6 +360,9 @@ static int tegra_gpio_resume(struct device *dev) > tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio)); > tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); > tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); > + tegra_gpio_writel(bank->dbc_cnt[p], GPIO_DBC_CNT(gpio)); > + tegra_gpio_writel(bank->dbc_enb[p], > + GPIO_MSK_DBC_EN(gpio)); If these registers are not valid on Tegra devices prior to Tegra210, I don't think we should write to these locations on those devices (even if we are writing back the values read). > @@ -351,6 +387,10 @@ static int tegra_gpio_suspend(struct device *dev) > bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio)); > bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio)); > bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio)); > + bank->dbc_enb[p] = tegra_gpio_readl( > + GPIO_MSK_DBC_EN(gpio)); > + bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) || > + bank->dbc_enb[p]; Same here, not sure we should even bother reading these for Tegra's before Tegra210. Cheers Jon
