On Thu, Jan 14, 2016 at 02:24:37PM -0500, Rhyland Klein wrote: > While enabling PLLE on both Tegra114 and Tegra210, we should be clearing > PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting > them. This patch fixes both places where we incorrectly set instead > of cleared those bits. > > Signed-off-by: Rhyland Klein <rkl...@nvidia.com> > --- > drivers/clk/tegra/clk-pll.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-)
Applied, thanks. Thierry
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