Re: Availability of kdb

[Jamie Lokier]

Jeff V. Merkey wrote:
> The best info I know of is to get an analyser that plugs into the
> processor socket (like an american arium) and enable branch trace
> messaging to monitor the interaction between the processor and the cache
> controllers.  You get info that's not in any Intel book just watching
> the thing run.  Nasty complicated stuff.  They explain some of it in the
> cache controller architecture manuals -- these are public.

I still don't see how processor traces will tell me what ordering
guarantees I can rely on across the range of processors.

-- Jamie
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