The best info I know of is to get an analyser that plugs into the
processor socket (like an american arium) and enable branch trace
messaging to monitor the interaction between the processor and the cache
controllers. You get info that's not in any Intel book just watching
the thing run. Nasty complicated stuff. They explain some of it in the
cache controller architecture manuals -- these are public.
:-)
Jeff
Jamie Lokier wrote:
>
> > I won't use a Linus example in the future since this seems to turn off
> > some folks reason centers and they go into "attack mode".
>
> Thanks Jeff, I heard that.
>
> I got a lot of useful info from that 3 week long thread, but it's still
> a bit confusing. A decent document from Intel or their competitors
> would still be good...
>
> -- Jamie
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