This commit adds a dt-bindings document of PECI adapter driver for ASPEED
AST24xx/25xx SoCs.

Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Joel Stanley <j...@jms.id.au>
Cc: Andrew Jeffery <and...@aj.id.au>
Cc: Benjamin Herrenschmidt <b...@kernel.crashing.org>
Cc: Greg Kroah-Hartman <gre...@linuxfoundation.org>
Cc: Jason M Biils <jason.m.bi...@linux.intel.com>
Cc: Milton Miller II <milt...@us.ibm.com>
Cc: Pavel Machek <pa...@ucw.cz>
Cc: Robin Murphy <robin.mur...@arm.com>
Cc: Ryan Chen <ryan_c...@aspeedtech.com>
Signed-off-by: Jae Hyun Yoo <jae.hyun....@linux.intel.com>
Reviewed-by: Haiyue Wang <haiyue.w...@linux.intel.com>
Reviewed-by: James Feist <james.fe...@linux.intel.com>
Reviewed-by: Vernon Mauery <vernon.mau...@linux.intel.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
 .../devicetree/bindings/peci/peci-aspeed.txt  | 55 +++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/peci/peci-aspeed.txt

diff --git a/Documentation/devicetree/bindings/peci/peci-aspeed.txt 
b/Documentation/devicetree/bindings/peci/peci-aspeed.txt
new file mode 100644
index 000000000000..cdca73a3b7d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/peci/peci-aspeed.txt
@@ -0,0 +1,55 @@
+Device tree configuration for PECI buses on the AST24XX and AST25XX SoCs.
+
+Required properties:
+- compatible        : Should be one of:
+                       "aspeed,ast2400-peci"
+                       "aspeed,ast2500-peci"
+- reg               : Should contain PECI controller registers location and
+                     length.
+- #address-cells    : Should be <1> required to define a client address.
+- #size-cells       : Should be <0> required to define a client address.
+- interrupts        : Should contain PECI controller interrupt.
+- clocks            : Should contain clock source for PECI controller. Should
+                     reference the external oscillator clock in the second
+                     cell.
+- resets            : Should contain phandle to reset controller with the reset
+                     number in the second cell.
+- clock-frequency   : Should contain the operation frequency of PECI controller
+                     in units of Hz.
+                     187500 ~ 24000000
+
+Optional properties:
+- msg-timing        : Message timing negotiation period. This value will
+                     determine the period of message timing negotiation to be
+                     issued by PECI controller. The unit of the programmed
+                     value is four times of PECI clock period.
+                     0 ~ 255 (default: 1)
+- addr-timing       : Address timing negotiation period. This value will
+                     determine the period of address timing negotiation to be
+                     issued by PECI controller. The unit of the programmed
+                     value is four times of PECI clock period.
+                     0 ~ 255 (default: 1)
+- rd-sampling-point : Read sampling point selection. The whole period of a bit
+                     time will be divided into 16 time frames. This value will
+                     determine the time frame in which the controller will
+                     sample PECI signal for data read back. Usually in the
+                     middle of a bit time is the best.
+                     0 ~ 15 (default: 8)
+- cmd-timeout-ms    : Command timeout in units of ms.
+                     1 ~ 60000 (default: 1000)
+
+Example:
+       peci0: peci-bus@0 {
+               compatible = "aspeed,ast2500-peci";
+               reg = <0x0 0x60>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               interrupts = <15>;
+               clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
+               resets = <&syscon ASPEED_RESET_PECI>;
+               clock-frequency = <24000000>;
+               msg-timing = <1>;
+               addr-timing = <1>;
+               rd-sampling-point = <8>;
+               cmd-timeout-ms = <1000>;
+       };
-- 
2.19.1

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