This commit adds PECI bus/adapter node of AST24xx/AST25xx into
aspeed-g4 and aspeed-g5.

Cc: Rob Herring <robh...@kernel.org>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Joel Stanley <j...@jms.id.au>
Cc: Andrew Jeffery <and...@aj.id.au>
Cc: Jason M Biils <jason.m.bi...@linux.intel.com>
Cc: Ryan Chen <ryan_c...@aspeedtech.com>
Signed-off-by: Jae Hyun Yoo <jae.hyun....@linux.intel.com>
Reviewed-by: Haiyue Wang <haiyue.w...@linux.intel.com>
Reviewed-by: James Feist <james.fe...@linux.intel.com>
Reviewed-by: Vernon Mauery <vernon.mau...@linux.intel.com>
---
 arch/arm/boot/dts/aspeed-g4.dtsi | 26 ++++++++++++++++++++++++++
 arch/arm/boot/dts/aspeed-g5.dtsi | 26 ++++++++++++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 69f6b9d2e7e7..fa5c358e199c 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -29,6 +29,7 @@
                serial3 = &uart4;
                serial4 = &uart5;
                serial5 = &vuart;
+               peci0 = &peci0;
        };
 
        cpus {
@@ -317,6 +318,13 @@
                                };
                        };
 
+                       peci: bus@1e78b000 {
+                               compatible = "simple-bus";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges = <0x0 0x1e78b000 0x60>;
+                       };
+
                        uart2: serial@1e78d000 {
                                compatible = "ns16550a";
                                reg = <0x1e78d000 0x20>;
@@ -360,6 +368,24 @@
        };
 };
 
+&peci {
+       peci0: peci-bus@0 {
+               compatible = "aspeed,ast2400-peci";
+               reg = <0x0 0x60>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               interrupts = <15>;
+               clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
+               resets = <&syscon ASPEED_RESET_PECI>;
+               clock-frequency = <24000000>;
+               msg-timing = <1>;
+               addr-timing = <1>;
+               rd-sampling-point = <8>;
+               cmd-timeout-ms = <1000>;
+               status = "disabled";
+       };
+};
+
 &i2c {
        i2c_ic: interrupt-controller@0 {
                #interrupt-cells = <1>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index d107459fc0f8..63900714fbd7 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -29,6 +29,7 @@
                serial3 = &uart4;
                serial4 = &uart5;
                serial5 = &vuart;
+               peci0 = &peci0;
        };
 
        cpus {
@@ -377,6 +378,13 @@
                                };
                        };
 
+                       peci: bus@1e78b000 {
+                               compatible = "simple-bus";
+                               #address-cells = <1>;
+                               #size-cells = <1>;
+                               ranges = <0x0 0x1e78b000 0x60>;
+                       };
+
                        uart2: serial@1e78d000 {
                                compatible = "ns16550a";
                                reg = <0x1e78d000 0x20>;
@@ -420,6 +428,24 @@
        };
 };
 
+&peci {
+       peci0: peci-bus@0 {
+               compatible = "aspeed,ast2500-peci";
+               reg = <0x0 0x60>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               interrupts = <15>;
+               clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
+               resets = <&syscon ASPEED_RESET_PECI>;
+               clock-frequency = <24000000>;
+               msg-timing = <1>;
+               addr-timing = <1>;
+               rd-sampling-point = <8>;
+               cmd-timeout-ms = <1000>;
+               status = "disabled";
+       };
+};
+
 &i2c {
        i2c_ic: interrupt-controller@0 {
                #interrupt-cells = <1>;
-- 
2.19.1

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