On 2017-12-04 20:40, Rosen Penev wrote: > Qualcomm claims this improves the D-cache footprint. Origina commit message > below: > > From: Ben Menchaca <ben.mench...@qca.qualcomm.com> > Date: Fri, 7 Jun 2013 10:57:28 -0500 > Subject: [ag71xx] cluster/align structs for cache perf > > Cluster the frequently used, per-packet structures in ag71xx near > to each other, and cacheline-align them. Some other re-ordering > occurred to move "warmer" structures near the per-packet structures. > > Signed-off-by: Ben Menchaca <ben.mench...@qca.qualcomm.com> > Signed-off-by: Rosen Penev <ros...@gmail.com> Merged patches 2-4 to my staging tree.
Thanks, - Felix _______________________________________________ Lede-dev mailing list Lede-dev@lists.infradead.org http://lists.infradead.org/mailman/listinfo/lede-dev
