On Tue, 25 Nov 2008 16:59:00 +0200
Avi Kivity <[EMAIL PROTECTED]> wrote:
> That's actually better and could be used for the other emulations.
> Please disassemble x86_emulate.o and verify that there are three
> different shld instructions, one for each register size.
For generating the three shld instructions I need to do the following:
+/* Instruction has three operands like shld */
+#define __emulate_2op_cl(_op,_shift, _src, _dst,_eflags,_suffix)
\
+ do {
\
+ unsigned long _tmp;
\
+ __asm__ __volatile__ (
\
+ _PRE_EFLAGS("0", "5", "2")
\
+ _op _suffix" %4,%1 \n\t"
\
+ _POST_EFLAGS("0", "5", "2")
\
+ : "=m" (_eflags), "+r" (_dst), \
+ "=&r" (_tmp)
\
+ : "c" (_shift) , "r" (_src), "i" (EFLAGS_MASK) \
+ );
\
+ } while (0)
+
+#define emulate_2op_cl(_op, _shift, _src, _dst, _eflags) \
+ do { \
+ switch ((_dst).bytes) { \
+ case 2: { \
+ unsigned short shift = (_shift).val; \
+ unsigned short src = (_src).val; \
+ unsigned short dst = (_dst).val; \
+ __emulate_2op_cl(_op,shift, src,dst,_eflags,"w"); \
+ break; \
+ } \
+ case 4: { \
+ unsigned int shift = (_shift).val; \
+ unsigned int src = (_src).val; \
+ unsigned int dst = (_dst).val; \
+ __emulate_2op_cl(_op,shift, src,dst,_eflags,"l"); \
+ break; \
+ } \
+ case 8: { \
+ unsigned long shift = (_shift).val; \
+ unsigned long src = (_src).val; \
+ unsigned long dst = (_dst).val; \
+ ON64(__emulate_2op_cl(_op,shift, src,dst,_eflags,"q"));
\
+ break; \
+ } \
+ } \
+ } while (0)
+
Otherwise the code for "case 4:" cannot be generated. I've got:
Error: Incorrect register `%rax' used with `l' suffix
Is it correct? If yes I will repost patches that emulate shld/shrd instructions.
Guillaume
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