Hi Kiryl, On Wed, Jun 17, 2026 at 08:20:01PM +0100, Kiryl Shutsemau wrote: > - GICv3 pseudo-NMI (interrupt priority masking). Its cost is on the > interrupt mask/unmask hot path: local_irq_enable() becomes an > ICC_PMR_EL1 write plus a synchronising barrier, and exception > entry/exit save and restore the PMR, paid on every CPU whether or not > an NMI is ever delivered. In our measurements, enabling pseudo-NMI > costs up to ~5% on real workloads, and ~66% on a syscall-in-a-loop > microbenchmark. A fleet-wide ~5% regression is not acceptable, so > these systems run with pseudo-NMI disabled.
Does your firmware set ICC_CTLR_EL1.PMHE? I'd be curious to see the numbers if the DSB was omitted on the enable path. > This series adds a third delivery backend that costs nothing on the hot > path: SDEI. Firmware delivers an SDEI event into a CPU regardless of its > DAIF state, so interrupt masking stays the cheap PSTATE.DAIF operation and > the firmware round-trip is paid only at the rare moment a CPU must be > interrupted. The direction of travel is to deprecated SDEI. I wouldn't add more stuff on top of this interface. (I haven't looked at the patches yet; Marc/Mark/James are more knowledgeable than me in this area) -- Catalin
