https://bugs.kde.org/show_bug.cgi?id=431556
--- Comment #4 from ahashmi <assad.has...@linaro.org> --- (In reply to Julian Seward from comment #3) > The cases are distinguished as follows: > isD == True, bitQ == 1 => 2d > isD == False, bitQ == 1 => 4s > isD == False, bitQ == 0 => 2s > + isH == True, bitQ == 0 => 4h > + isH == False, bitQ == 1 => 8h > > Is this comment out of date? The function it applies to takes an > ARM64VecESize now, > not isH / isD. Ah yes! It is out-of-date. I'll remove. > + if (1) test_faddp_4h_00_00_00(TyH); > > The tests where the three register numbers are the same .. are they of any > value? In particular, they won't expose mixups where the wrong register > number is used in decode. Those cases are covered by the _N_N+1_N+2 variants > afaics. Is there some other reason to keep the N_N_N variants? The reason for the N_N_N variants is that they may flush out bugs to do with temporaries in IR. That's my simple minded motivation. If such bugs are not possible I can remove. -- You are receiving this mail because: You are watching all bug changes.
