https://bugs.kde.org/show_bug.cgi?id=431556
Julian Seward <jsew...@acm.org> changed:
What |Removed |Added
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CC| |jsew...@acm.org
--- Comment #3 from Julian Seward <jsew...@acm.org> ---
(In reply to ahashmi from comment #2)
> Created attachment 134852 [details]
> Patch completes addition of arm64 v8.2 faddp instructions.
Looks good to me; a couple of small queries, but basically is landable.
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The cases are distinguished as follows:
isD == True, bitQ == 1 => 2d
isD == False, bitQ == 1 => 4s
isD == False, bitQ == 0 => 2s
+ isH == True, bitQ == 0 => 4h
+ isH == False, bitQ == 1 => 8h
Is this comment out of date? The function it applies to takes an ARM64VecESize
now,
not isH / isD.
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+ if (1) test_faddp_4h_00_00_00(TyH);
The tests where the three register numbers are the same .. are they of any
value? In particular, they won't expose mixups where the wrong register
number is used in decode. Those cases are covered by the _N_N+1_N+2 variants
afaics. Is there some other reason to keep the N_N_N variants?
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