Hi,

On 11/7/18 2:55 PM, Liu, Yi L wrote:
Hi Baolu,

From: Lu Baolu [mailto:baolu...@linux.intel.com]
Sent: Monday, November 5, 2018 1:32 PM
Subject: [PATCH v4 05/12] iommu/vt-d: Reserve a domain id for FL and PT modes

Vt-d spec rev3.0 (section 6.2.3.1) requires that each pasid
entry for first-level or pass-through translation should be
programmed with a domain id different from those used for
second-level or nested translation. It is recommended that
software could use a same domain id for all first-only and
pass-through translations.

This reserves a domain id for first-level and pass-through
translations.

Cc: Ashok Raj <ashok....@intel.com>
Cc: Jacob Pan <jacob.jun....@linux.intel.com>
Cc: Kevin Tian <kevin.t...@intel.com>
Cc: Liu Yi L <yi.l....@intel.com>
Cc: Sanjay Kumar <sanjay.k.ku...@intel.com>
Signed-off-by: Lu Baolu <baolu...@linux.intel.com>
---
  drivers/iommu/intel-iommu.c | 10 ++++++++++
  drivers/iommu/intel-pasid.h |  6 ++++++
  2 files changed, 16 insertions(+)

diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 9331240c70b8..2f7455ee4e7a 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -1618,6 +1618,16 @@ static int iommu_init_domains(struct intel_iommu
*iommu)
         */
        set_bit(0, iommu->domain_ids);

+       /*
+        * Vt-d spec rev3.0 (section 6.2.3.1) requires that each pasid
+        * entry for first-level or pass-through translation modes should
+        * be programmed with a domain id different from those used for
+        * second-level or nested translation. We reserve a domain id for
+        * this purpose.
+        */
+       if (sm_supported(iommu))
+               set_bit(FLPT_DEFAULT_DID, iommu->domain_ids);

"FLPT_DEFAULT_DID" looks very likely for first level translation. How about
"PT_FL_DEFAULT_DID"?

We have comments above it, so people won't be confused.


        return 0;
  }

diff --git a/drivers/iommu/intel-pasid.h b/drivers/iommu/intel-pasid.h
index 12f480c2bb8b..03c1612d173c 100644
--- a/drivers/iommu/intel-pasid.h
+++ b/drivers/iommu/intel-pasid.h
@@ -17,6 +17,12 @@
  #define PDE_PFN_MASK                  PAGE_MASK
  #define PASID_PDE_SHIFT                       6

+/*
+ * Domain ID reserved for pasid entries programmed for first-level
+ * only and pass-through transfer modes.
+ */
+#define FLPT_DEFAULT_DID               1

Would be helpful to elaborate why DID 1 is selected in the patch
description.

Yeah. DID 0 has been caved out for caching mode and we start from 1 for
this.

Best regards,
Lu Baolu
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