On 11/04/17 15:42, linucher...@gmail.com wrote:
> From: Linu Cherian <linu.cher...@cavium.com>
>
> Add SMMuV3 model definitions.
>
> Signed-off-by: Linu Cherian <linu.cher...@cavium.com>
> ---
> include/acpi/actbl2.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
> index 2b4af07..9db67d6 100644
> --- a/include/acpi/actbl2.h
> +++ b/include/acpi/actbl2.h
> @@ -778,6 +778,11 @@ struct acpi_iort_smmu {
> #define ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002 /* ARM Corelink MMU-400
> */
> #define ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003 /* ARM Corelink MMU-500
> */
>
> +#define ACPI_IORT_SMMU_V3 0x00000000 /* Generic SMMUv3 */
> +#define ACPI_IORT_SMMU_CORELINK_MMU600 0x00000001 /* ARM Corelink
> MMU-600 */
> +#define ACPI_IORT_SMMU_V3_HISILICON 0x00000002 /* HiSilicon SMMUv3
> */
> +#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000003 /* Cavium CN99xx
> SMMUv3 */
None of those models are listed in the current IORT spec.
What's MMU-600?
Robin.
> +
> /* Masks for Flags field above */
>
> #define ACPI_IORT_SMMU_DVM_SUPPORTED (1)
>
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