To ensure proper operation, wait for 10 to 20 microseconds before
enabling TSPLL.
Adjust wait time after enabling TSPLL from 1-5 ms to 1-2 ms.
Those values are empirical and tested on multiple HW configurations.
Reviewed-by: Milena Olech <milena-ol...@intel.com>
Signed-off-by: Karol Kolacinski <karol.kolacin...@intel.com>
---
drivers/net/ethernet/intel/ice/ice_tspll.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c
b/drivers/net/ethernet/intel/ice/ice_tspll.c
index dce5164ebd9b..62da095d32ef 100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -222,12 +222,15 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum
ice_tspll_freq clk_freq,
r24 |= FIELD_PREP(ICE_CGU_R23_R24_TIME_REF_SEL, clk_src);
ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, r24);
+ /* Wait to ensure everything is stable */
+ usleep_range(10, 20);
+
/* Finally, enable the PLL */
r24 |= ICE_CGU_R23_R24_TSPLL_ENABLE;
ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, r24);
- /* Wait to verify if the PLL locks */
- usleep_range(1000, 5000);
+ /* Wait at least 1 ms to verify if the PLL locks */
+ usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_RO_BWM_LF, &val);
if (!(val & ICE_CGU_RO_BWM_LF_TRUE_LOCK)) {
@@ -348,12 +351,15 @@ static int ice_tspll_cfg_e825c(struct ice_hw *hw, enum
ice_tspll_freq clk_freq,
/* Clear the R24 register. */
ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, 0);
+ /* Wait to ensure everything is stable */
+ usleep_range(10, 20);
+
/* Finally, enable the PLL */
r23 |= ICE_CGU_R23_R24_TSPLL_ENABLE;
ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R23, r23);
- /* Wait to verify if the PLL locks */
- usleep_range(1000, 5000);
+ /* Wait at least 1 ms to verify if the PLL locks */
+ usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_RO_LOCK, &val);
if (!(val & ICE_CGU_RO_LOCK_TRUE_LOCK)) {
--
2.48.1
