On Fri, Feb 07, 2025 at 07:02:53PM +0100, Arkadiusz Kubalewski wrote: > From: Karol Kolacinski <karol.kolacin...@intel.com> > > This change aligns E810 PTP pin control to all other products. > > Currently, SMA/U.FL port expanders are controlled together with SDP pins > connected to 1588 clock. To align this, separate this control by > exposing only SDP20..23 pins in PTP API on adapters with DPLL. > > Clear error for all E810 on absent NVM pin section or other errors to > allow proper initialization on SMA E810 with NVM section. > > Use ARRAY_SIZE for pin array instead of internal definition. > > Reviewed-by: Milena Olech <milena.ol...@intel.com> > Signed-off-by: Karol Kolacinski <karol.kolacin...@intel.com> > Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalew...@intel.com>
Reviewed-by: Simon Horman <ho...@kernel.org>
