On Fri, Feb 07, 2025 at 07:02:52PM +0100, Arkadiusz Kubalewski wrote: > DPLL-enabled E810 NIC driver provides user with list of input and output > pins. Hardware internal design impacts user control over SMA and U.FL > pins. Currently end-user view on those dpll pins doesn't provide any layer > of abstraction. On the hardware level SMA and U.FL pins are tied together > due to existence of direction control logic for each pair: > - SMA1 (bi-directional) and U.FL1 (only output) > - SMA2 (bi-directional) and U.FL2 (only input) > The user activity on each pin of the pair may impact the state of the > other. > > Previously all the pins were provided to the user as is, without the > control over SMA pins direction. > > Introduce a software controlled layer of abstraction over external board > pins, instead of providing the user with access to raw pins connected to > the dpll: > - new software controlled SMA and U.FL pins, > - callback operations directing user requests to corresponding hardware > pins according to the runtime configuration, > - ability to control SMA pins direction. > > Reviewed-by: Przemek Kitszel <przemyslaw.kits...@intel.com> > Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalew...@intel.com>
Reviewed-by: Simon Horman <ho...@kernel.org>
