On 9/22/2023 04:40, Vinicius Costa Gomes wrote:
Add support for using Timer 1 (i225/i226 have 4 timer registers) as a
free-running clock (the "cycles" clock) in addition to Timer 0 (the
default, "adjustable clock"). The objective is to allow taprio/etf
offloading to coexist with PTP vclocks.
Besides the implementation of .getcyclesx64() for i225/i226, to keep
timestamping working when vclocks are in use, we also need to add
support for TX and RX timestamping using the free running timer, when
the requesting socket is bound to a vclock.
On the RX side, i225/i226 can be configured to store the values of two
timers in the received packet metadata area, so it's a matter of
configuring the right registers and retrieving the right timestamp.
The TX is a bit more involved because the hardware stores a single
timestamp (with the selected timer in the TX descriptor) into one of
the timestamp registers.
Note some changes at how the timestamps are done for RX, the
conversion and adjustment of timestamps are now done closer to the
consumption of the timestamp instead of near the reception.
Signed-off-by: Vinicius Costa Gomes <vinicius.go...@intel.com>
---
drivers/net/ethernet/intel/igc/igc.h | 21 ++++++++++-
drivers/net/ethernet/intel/igc/igc_base.h | 4 ++
drivers/net/ethernet/intel/igc/igc_defines.h | 2 +
drivers/net/ethernet/intel/igc/igc_main.c | 55 ++++++++++++++++++++--------
drivers/net/ethernet/intel/igc/igc_ptp.c | 50 +++++++++++++++----------
drivers/net/ethernet/intel/igc/igc_regs.h | 5 +++
6 files changed, 101 insertions(+), 36 deletions(-)
Tested-by: Naama Meir <naamax.m...@linux.intel.com>
_______________________________________________
Intel-wired-lan mailing list
Intel-wired-lan@osuosl.org
https://lists.osuosl.org/mailman/listinfo/intel-wired-lan
