On Fri, 2016-05-13 at 23:41 +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> Rather than having a BXT specific function to make sure the DE PLL is
> enabled after disabling DC6, let's just make sure the current cdclk
> is the same as what we last programmed.
>
> Having another check in bxt_display_core_init() almost immediately after
> the cdclk init seems redundant, so let's just kill that one.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 15 ---------------
> drivers/gpu/drm/i915/intel_drv.h | 1 -
> drivers/gpu/drm/i915/intel_runtime_pm.c | 8 ++++----
> 3 files changed, 4 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 14bc14c7827b..9725ba59716e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5490,21 +5490,6 @@ static void broxton_set_cdclk(struct drm_i915_private
> *dev_priv, int cdclk)
> intel_update_cdclk(dev_priv->dev);
> }
>
> -static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv)
> -{
> - if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE))
> - return false;
> -
> - /* TODO: Check for a valid CDCLK rate */
> -
> - return true;
> -}
> -
> -bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv)
> -{
> - return broxton_cdclk_is_enabled(dev_priv);
> -}
> -
> void broxton_init_cdclk(struct drm_i915_private *dev_priv)
> {
> intel_update_cdclk(dev_priv->dev);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 319e52278d1f..f1f4bde4108d 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1270,7 +1270,6 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> void broxton_init_cdclk(struct drm_i915_private *dev_priv);
> void broxton_uninit_cdclk(struct drm_i915_private *dev_priv);
> -bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv);
> void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
> void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
> void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6817a3cb5fbc..b70e123f67ca 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -811,10 +811,11 @@ static void gen9_dc_off_power_well_enable(struct
> drm_i915_private *dev_priv,
> {
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> - if (IS_BROXTON(dev_priv)) {
> - broxton_cdclk_verify_state(dev_priv);
> + WARN_ON(dev_priv->cdclk_freq !=
> + dev_priv->display.get_display_clock_speed(dev_priv->dev));
> +
> + if (IS_BROXTON(dev_priv))
> broxton_ddi_phy_verify_state(dev_priv);
> - }
> }
>
> static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> @@ -2288,7 +2289,6 @@ void bxt_display_core_init(struct drm_i915_private
> *dev_priv,
>
> broxton_ddi_phy_init(dev_priv);
>
> - broxton_cdclk_verify_state(dev_priv);
> broxton_ddi_phy_verify_state(dev_priv);
>
> if (resume && dev_priv->csr.dmc_payload)
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