On pe, 2016-05-13 at 23:41 +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> Future platforms will have multiple options for the cdclk PLL reference
> clock, so let's start tracking that under dev_priv alreday on SKL,
> although on SKL it's always 24 MHz.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 14 ++++++++------
> 2 files changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8da787cd2227..422f219450c1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1828,7 +1828,7 @@ struct drm_i915_private {
> unsigned int czclk_freq;
>
> struct {
> - unsigned int vco;
> + unsigned int vco, ref;
> } cdclk_pll;
>
> /**
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 8bde3ae34869..11e90863533b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5335,8 +5335,9 @@ static void intel_update_cdclk(struct drm_device *dev)
> dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
>
> if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
> - DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz\n",
> - dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco);
> + DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz,
> ref: %d kHz\n",
> + dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
> + dev_priv->cdclk_pll.ref);
> else
> DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
> dev_priv->cdclk_freq);
> @@ -5542,6 +5543,8 @@ skl_dpll0_update(struct drm_i915_private *dev_priv)
> {
> u32 val;
>
> + dev_priv->cdclk_pll.ref = 24000;
> +
> val = I915_READ(LCPLL1_CTL);
> if ((val & LCPLL_PLL_ENABLE) == 0) {
> dev_priv->cdclk_pll.vco = 0;
> @@ -5730,7 +5733,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private
> *dev_priv);
>
> void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
> {
> - skl_set_cdclk(dev_priv, 24000, 0);
> + skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
> }
>
> void skl_init_cdclk(struct drm_i915_private *dev_priv)
> @@ -6646,7 +6649,7 @@ static int skylake_get_display_clock_speed(struct
> drm_device *dev)
> skl_dpll0_update(dev_priv);
>
> if (dev_priv->cdclk_pll.vco == 0)
> - return 24000; /* 24MHz is the cd freq with NSSC ref */
> + return dev_priv->cdclk_pll.ref;
>
> cdctl = I915_READ(CDCLK_CTL);
>
> @@ -6678,8 +6681,7 @@ static int skylake_get_display_clock_speed(struct
> drm_device *dev)
> }
> }
>
> - /* error case, do as if DPLL0 isn't enabled */
> - return 24000;
> + return dev_priv->cdclk_pll.ref;
> }
>
> static int broxton_get_display_clock_speed(struct drm_device *dev)
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