On Tue, 05 Jan 2016, Rodrigo Vivi <rodrigo.v...@intel.com> wrote:
> No functional changes with this patch. The idea is just to organize
> the platform features in a standard place making new platform aditions
> easily and possible to see all the present features of the platform on
> the intel info dumped information at dmesg.
>
> Also for this one it is better to put the ones that support than
> skip for every atom based platform.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 ++
> drivers/gpu/drm/i915/i915_drv.h | 5 ++---
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index cb8adb5..ed34164 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -218,6 +218,7 @@ static const struct intel_device_info
> intel_sandybridge_m_info = {
> .need_gfx_hws = 1, .has_hotplug = 1,
> .has_fbc = 1,
> .has_runtime_pm = 1,
> + .has_core_ring_freq = 1,
Missing for sandybridge_d?
BR,
Jani.
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
> .has_llc = 1,
> GEN_DEFAULT_PIPEOFFSETS,
> @@ -228,6 +229,7 @@ static const struct intel_device_info
> intel_sandybridge_m_info = {
> .gen = 7, .num_pipes = 3, \
> .need_gfx_hws = 1, .has_hotplug = 1, \
> .has_fbc = 1, \
> + .has_core_ring_freq = 1, \
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
> .has_llc = 1, \
> GEN_DEFAULT_PIPEOFFSETS, \
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8143a51..cb08d7d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -765,6 +765,7 @@ struct intel_csr {
> func(has_fbc) sep \
> func(has_psr) sep \
> func(has_runtime_pm) sep \
> + func(has_core_ring_freq) sep \
> func(has_pipe_cxsr) sep \
> func(has_hotplug) sep \
> func(cursor_needs_physical) sep \
> @@ -2619,9 +2620,7 @@ struct drm_i915_cmd_table {
> #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
> INTEL_INFO(dev)->gen >= 8)
>
> -#define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
> - !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
> - !IS_BROXTON(dev))
> +#define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->has_core_ring_freq)
>
> #define INTEL_PCH_DEVICE_ID_MASK 0xff00
> #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
--
Jani Nikula, Intel Open Source Technology Center
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