On Tue, Feb 10, 2015 at 10:31:00AM +0000, Damien Lespiau wrote:
> v2: Reorder defines (Ben)
> v3: More bikesheds, this time re-ordering comments! (Chris)
>
> Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
> Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Signed-off-by: Damien Lespiau <damien.lesp...@intel.com>
Queued for -next, thanks for the patch.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 +++++---
> 2 files changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b4abd50..4b8450d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5273,10 +5273,11 @@ enum skl_disp_power_wells {
>
> /* GEN8 chicken */
> #define HDC_CHICKEN0 0x7300
> -#define HDC_FORCE_NON_COHERENT (1<<4)
> -#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
> #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
> +#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
> #define HDC_BARRIER_PERFORMANCE_DISABLE (1<<10)
> +#define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1<<5)
> +#define HDC_FORCE_NON_COHERENT (1<<4)
>
> /* WaCatErrorRejectionIssue */
> #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 93365fe..443e19c 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -788,12 +788,14 @@ static int bdw_init_workarounds(struct intel_engine_cs
> *ring)
> * workaround for for a possible hang in the unlikely event a TLB
> * invalidation occurs during a PSD flush.
> */
> - /* WaForceEnableNonCoherent:bdw */
> - /* WaHdcDisableFetchWhenMasked:bdw */
> - /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
> WA_SET_BIT_MASKED(HDC_CHICKEN0,
> + /* WaForceEnableNonCoherent:bdw */
> HDC_FORCE_NON_COHERENT |
> + /* WaForceContextSaveRestoreNonCoherent:bdw */
> + HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
> + /* WaHdcDisableFetchWhenMasked:bdw */
> HDC_DONOT_FETCH_MEM_WHEN_MASKED |
> + /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
> (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
>
> /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
> --
> 1.8.3.1
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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