From: Jeff McGee <jeff.mc...@intel.com>
Cherryview fusing allows for different EU totals within a single
device ID, so fused-based detection is a must. Go ahead and determine
subslice total from fuse as well just in case. Slice total and
threads per EU are fixed for all CHV.
For: VIZ-4636
Signed-off-by: Jeff McGee <jeff.mc...@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++++++
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a6634e6..0ab8f3a 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -618,6 +618,24 @@ static void intel_device_info_runtime_init(struct
drm_device *dev)
info->num_pipes = 0;
}
}
+
+ /* Initialize required GT attributes info */
+ if (IS_CHERRYVIEW(dev)) {
+ u32 reg, ss_dis, eu_dis;
+
+ reg = I915_READ(CHV_FUSE_GT);
+ ss_dis = reg & (CHV_FGT_DISABLE_SS0 |
+ CHV_FGT_DISABLE_SS1);
+ eu_dis = reg & (CHV_FGT_EU_DIS_SS0_R0_MASK |
+ CHV_FGT_EU_DIS_SS0_R1_MASK |
+ CHV_FGT_EU_DIS_SS1_R0_MASK |
+ CHV_FGT_EU_DIS_SS1_R1_MASK);
+
+ info->slice_total = 1;
+ info->subslice_total = 2 - hweight32(ss_dis);
+ info->eu_total = 16 - hweight32(eu_dis);
+ info->threads_per_eu = 7;
+ }
}
/**
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 40ca873..f60119c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6127,6 +6127,19 @@ enum punit_power_well {
#define GEN7_MISCCPCTL (0x9424)
#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
+/* Fuse readout registers for GT */
+#define CHV_FUSE_GT 0x182168
+#define CHV_FGT_DISABLE_SS0 10
+#define CHV_FGT_DISABLE_SS1 11
+#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
+#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
+#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
+#define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT)
+#define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24
+#define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT)
+#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
+#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
#define HSW_L3CDERRST11 0xB208 /* L3CD Error Status
register 1 slice 1 */
--
2.2.0
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