From: Jeff McGee <jeff.mc...@intel.com>
Broadwell values could be tabulated by device ID, but we go ahead
and detect from fuses because it is easier and more flexible.
For: VIZ-4636
Signed-off-by: Jeff McGee <jeff.mc...@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 20 +++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 11 +++++++++++
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 0ab8f3a..023d010 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -620,7 +620,25 @@ static void intel_device_info_runtime_init(struct
drm_device *dev)
}
/* Initialize required GT attributes info */
- if (IS_CHERRYVIEW(dev)) {
+ if (IS_BROADWELL(dev)) {
+ u32 fuse2, eu_dis0, eu_dis1, eu_dis2, s_ena, ss_dis;
+
+ fuse2 = I915_READ(GEN8_FUSE2);
+ eu_dis0 = I915_READ(GEN8_EU_DISABLE0);
+ eu_dis1 = I915_READ(GEN8_EU_DISABLE1);
+ eu_dis2 = I915_READ(GEN8_EU_DISABLE2);
+ s_ena = fuse2 & GEN8_F2_S_ENA_MASK;
+ ss_dis = fuse2 & GEN8_F2_SS_DIS_MASK;
+ eu_dis2 &= GEN8_EU_DIS2_S2_SS2_MASK;
+
+ info->slice_total = hweight32(s_ena);
+ info->subslice_total = (3 - hweight32(ss_dis)) *
+ info->slice_total;
+ info->eu_total = 72 - (hweight32(eu_dis0) +
+ hweight32(eu_dis1) +
+ hweight32(eu_dis2));
+ info->threads_per_eu = 7;
+ } else if (IS_CHERRYVIEW(dev)) {
u32 reg, ss_dis, eu_dis;
reg = I915_READ(CHV_FUSE_GT);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f60119c..b08747c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6140,6 +6140,17 @@ enum punit_power_well {
#define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28
#define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT)
+#define GEN8_FUSE2 0x9120
+#define GEN8_F2_SS_DIS_SHIFT 21
+#define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT)
+#define GEN8_F2_S_ENA_SHIFT 25
+#define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT)
+
+#define GEN8_EU_DISABLE0 0x9134
+#define GEN8_EU_DISABLE1 0x9138
+#define GEN8_EU_DISABLE2 0x913c
+#define GEN8_EU_DIS2_S2_SS2_MASK (0xff)
+
/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
#define HSW_L3CDERRST11 0xB208 /* L3CD Error Status
register 1 slice 1 */
--
2.2.0
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