>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Rodrigo Vivi
>Sent: Friday, November 14, 2014 10:23 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 14/15] drm/i915: VLV/CHV PSR debugfs.
>
>Add debugfs support for Valleyview and Cherryview considering that
>we have PSR per pipe and we don't have any kind of
>performance counter as we have on other platforms that support PSR.
>
>Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
>---
> drivers/gpu/drm/i915/i915_debugfs.c | 34 +++++++++++++++++++++++++++++-----
> 1 file changed, 29 insertions(+), 5 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>b/drivers/gpu/drm/i915/i915_debugfs.c
>index 319da61..d9b27f8 100644
>--- a/drivers/gpu/drm/i915/i915_debugfs.c
>+++ b/drivers/gpu/drm/i915/i915_debugfs.c
>@@ -2126,6 +2126,8 @@ static int i915_edp_psr_status(struct seq_file *m, void
>*data)
> struct drm_device *dev = node->minor->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> u32 psrperf = 0;
>+ u32 stat[3];
>+ enum pipe pipe;
> bool enabled = false;
>
> intel_runtime_pm_get(dev_priv);
>@@ -2140,14 +2142,36 @@ static int i915_edp_psr_status(struct seq_file *m,
>void *data)
> seq_printf(m, "Re-enable work scheduled: %s\n",
> yesno(work_busy(&dev_priv->psr.work.work)));
>
>- enabled = HAS_PSR(dev) &&
>- I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
>- seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
>+ if (HAS_PSR(dev)) {
>+ if (HAS_DDI(dev))
>+ enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
>+ else {
>+ for_each_pipe(dev_priv, pipe) {
>+ stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
>+ VLV_EDP_PSR_CURR_STATE_MASK;
>+ if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP)
>||
>+ (stat[pipe] ==
>VLV_EDP_PSR_ACTIVE_SF_UPDATE))
>+ enabled = true;
>+ }
>+ }
>+ }
Reviewed-by: Durgadoss R <durgados...@intel.com>
Thanks,
Durga
>+ seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
>
>- if (HAS_PSR(dev))
>+ if (!HAS_DDI(dev))
>+ for_each_pipe(dev_priv, pipe) {
>+ if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
>+ (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
>+ seq_printf(m, " pipe %c", pipe_name(pipe));
>+ }
>+ seq_puts(m, "\n");
>+
>+ /* CHV PSR has no kind of performance counter */
>+ if (HAS_PSR(dev) && HAS_DDI(dev)) {
> psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
> EDP_PSR_PERF_CNT_MASK;
>- seq_printf(m, "Performance_Counter: %u\n", psrperf);
>+
>+ seq_printf(m, "Performance_Counter: %u\n", psrperf);
>+ }
> mutex_unlock(&dev_priv->psr.lock);
>
> intel_runtime_pm_put(dev_priv);
>--
>1.9.3
>
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