On Thu, Nov 13, 2014 at 07:33:21PM -0500, Rodrigo Vivi wrote: > On Thu, Nov 6, 2014 at 1:32 PM, R, Durgadoss <durgados...@intel.com> wrote: > > I see we are keeping the source active during PSR. > > Making this '0' may provide better power savings, > > but we need to manage a lot of hassle during PSR exit.. > > (like Link training, DPIO/PLL bring up etc..) > > Also I think this blocked sink crc to work. So we wouldn't be able to > validate it. > Although there are other things blocking that tests :( > But I can double check that anyway.
Well we only need to wake up dp aux to get the sink crc, which should just be the power well. There shouldn't be any need to wake up the source port at all. So I don't expect big issues here if we do this. Yeah, I'm an optimist as ever ;-) -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
