Oh just noticed we duplicated effort on this.. [5/5] drm/i915/bdw: Remove BDW preproduction W/As until C stepping.
After this land -nightly I rebase my series on top. On Wed, Sep 24, 2014 at 1:41 AM, Daniel Vetter <dan...@ffwll.ch> wrote: > On Tue, Sep 23, 2014 at 02:48:47PM +0300, Jani Nikula wrote: > > On Tue, 23 Sep 2014, Daniel Vetter <dan...@ffwll.ch> wrote: > > > On Fri, Sep 19, 2014 at 08:49:06PM +0300, Ville Syrjälä wrote: > > >> On Fri, Sep 19, 2014 at 08:05:26PM +0300, Mika Kuoppala wrote: > > >> > as these have been fixed in production hw and hurt performance > > >> > if applied. > > >> > > > >> > v2: adjust requested ring space (Ville) > > >> > > > >> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83482 > > >> > Tested-by: zhoujian <jianx.z...@intel.com> > > >> > Signed-off-by: Mika Kuoppala <mika.kuopp...@intel.com> > > >> > > >> Documentation agrees that these can go. > > >> Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com> > > > > > > Cc: sta...@vger.kernel.org imo. Jani? > > > > This depends on > > > > commit 86d7f23842f1bce3ab5e8c8d0c676112bbc4c99b > > Author: Arun Siluvery <arun.siluv...@linux.intel.com> > > Date: Tue Aug 26 14:44:50 2014 +0100 > > > > drm/i915/bdw: Apply workarounds in render ring init function > > > > which brought the problem to daylight to begin with. That's not in > > 3.17-rc6. I'm not sure if that one has additional dependencies, but > > perhaps a combined backport without an intermediate broken step is > > plausible. > > > > In any case I don't think this is something we want to rush for 3.17 > > now, since a release is imminent, so it'll be 3.18. Adding cc: stable is > > up to you, but do note the size is beyond stable rules. > > Hm right, so a patch for drm-intel-next-fixes (first one even!). I'll > leave out the cc: stable since backporting all the register wa stuff is a > pile of patches ... > -Daniel > > > > > > > BR, > > Jani. > > > > > > > > > -Daniel > > > > > >> > > >> > --- > > >> > drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++------------- > > >> > 1 file changed, 2 insertions(+), 13 deletions(-) > > >> > > > >> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > b/drivers/gpu/drm/i915/intel_ringbuffer.c > > >> > index 681ea86..679a3c7 100644 > > >> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > >> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > >> > @@ -707,7 +707,7 @@ static int bdw_init_workarounds(struct > intel_engine_cs *ring) > > >> > * update the number of dwords required based on the > > >> > * actual number of workarounds applied > > >> > */ > > >> > - ret = intel_ring_begin(ring, 24); > > >> > + ret = intel_ring_begin(ring, 18); > > >> > if (ret) > > >> > return ret; > > >> > > > >> > @@ -722,19 +722,8 @@ static int bdw_init_workarounds(struct > intel_engine_cs *ring) > > >> > intel_ring_emit_wa(ring, GEN7_ROW_CHICKEN2, > > >> > > _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); > > >> > > > >> > - /* > > >> > - * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for > > >> > - * pre-production hardware > > >> > - */ > > >> > intel_ring_emit_wa(ring, HALF_SLICE_CHICKEN3, > > >> > - > _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS > > >> > - | > GEN8_SAMPLER_POWER_BYPASS_DIS)); > > >> > - > > >> > - intel_ring_emit_wa(ring, GEN7_HALF_SLICE_CHICKEN1, > > >> > - > _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); > > >> > - > > >> > - intel_ring_emit_wa(ring, COMMON_SLICE_CHICKEN2, > > >> > - > _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); > > >> > + > _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); > > >> > > > >> > /* Use Force Non-Coherent whenever executing a 3D context. > This is a > > >> > * workaround for for a possible hang in the unlikely > event a TLB > > >> > -- > > >> > 1.9.1 > > >> > > >> -- > > >> Ville Syrjälä > > >> Intel OTC > > >> _______________________________________________ > > >> Intel-gfx mailing list > > >> Intel-gfx@lists.freedesktop.org > > >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > -- > > > Daniel Vetter > > > Software Engineer, Intel Corporation > > > +41 (0) 79 365 57 48 - http://blog.ffwll.ch > > > > -- > > Jani Nikula, Intel Open Source Technology Center > > -- > Daniel Vetter > Software Engineer, Intel Corporation > +41 (0) 79 365 57 48 - http://blog.ffwll.ch > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > -- Rodrigo Vivi Blog: http://blog.vivi.eng.br
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