> -----Original Message-----
> From: Borah, Chaitanya Kumar <[email protected]>
> Sent: 15 July 2026 18:45
> To: Golani, Mitulkumar Ajitkumar <[email protected]>;
> [email protected]
> Cc: [email protected]; Shankar, Uma <[email protected]>;
> Nautiyal, Ankit K <[email protected]>
> Subject: Re: [PATCH v3 5/8] drm/i915/vrr: Move CMRR hw registers to fix
> refresh rate path
>
>
>
> On 7/14/2026 4:09 PM, Mitul Golani wrote:
> > Move CMRR register writes to fix refresh rate register write path to
> > consolidate with fix refresh rate implementation.
> >
> > Signed-off-by: Mitul Golani <[email protected]>
> > ---
> > drivers/gpu/drm/i915/display/intel_vrr.c | 22 +++++++++++-----------
> > 1 file changed, 11 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> > b/drivers/gpu/drm/i915/display/intel_vrr.c
> > index 25ce56d48bb1..95c7b0c05ec3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> > @@ -337,6 +337,17 @@ void intel_vrr_set_fixed_rr_timings(const struct
> intel_crtc_state *crtc_state,
> > if (!intel_vrr_possible(crtc_state))
> > return;
> >
> > + if (crtc_state->vrr.cmrr.enable) {
> > + intel_de_write(display, TRANS_CMRR_M_HI(display,
> transcoder),
> > + upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> > + intel_de_write(display, TRANS_CMRR_M_LO(display,
> transcoder),
> > + lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> > + intel_de_write(display, TRANS_CMRR_N_HI(display,
> transcoder),
> > + upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> > + intel_de_write(display, TRANS_CMRR_N_LO(display,
> transcoder),
> > + lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
>
> Shouldn't TRANS_CMRR_N_HI be the last register to be written.
No functional change has done, just moved to fix refresh rate path.
In later patches when actual enable/disable sequence is computed, there
suggested changes are applied.
Thanks
>
> > + }
> > +
> > intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
> > intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
> > intel_de_write(display, TRANS_VRR_VMAX(display, transcoder), @@
> > -648,17 +659,6 @@ void intel_vrr_set_transcoder_timings(const struct
> intel_crtc_state *crtc_state)
> > return;
> > }
> >
> > - if (crtc_state->vrr.cmrr.enable) {
> > - intel_de_write(display, TRANS_CMRR_M_HI(display,
> cpu_transcoder),
> > - upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> > - intel_de_write(display, TRANS_CMRR_M_LO(display,
> cpu_transcoder),
> > - lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
> > - intel_de_write(display, TRANS_CMRR_N_HI(display,
> cpu_transcoder),
> > - upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> > - intel_de_write(display, TRANS_CMRR_N_LO(display,
> cpu_transcoder),
> > - lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
> > - }
> > -
> > intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
> > intel_cmtg_set_vrr_timings(crtc_state);
> >
