On Wed, 09 Apr 2014, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> Fill in the sprite bits for DDL1/DDL2 registers, and add DDL3.
>
> Still need to write the code to use these...
>
Reviewed-by: Jani Nikula <jani.nik...@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 98f549a..c7ec7d6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3552,14 +3552,43 @@ enum punit_power_well {
> #define DDL_CURSORA_PRECISION_32 (1<<31)
> #define DDL_CURSORA_PRECISION_16 (0<<31)
> #define DDL_CURSORA_SHIFT 24
> +#define DDL_SPRITEB_PRECISION_32 (1<<23)
> +#define DDL_SPRITEB_PRECISION_16 (0<<23)
> +#define DDL_SPRITEB_SHIFT 16
> +#define DDL_SPRITEA_PRECISION_32 (1<<15)
> +#define DDL_SPRITEA_PRECISION_16 (0<<15)
> +#define DDL_SPRITEA_SHIFT 8
> #define DDL_PLANEA_PRECISION_32 (1<<7)
> #define DDL_PLANEA_PRECISION_16 (0<<7)
> +#define DDL_PLANEA_SHIFT 0
> +
> #define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
> #define DDL_CURSORB_PRECISION_32 (1<<31)
> #define DDL_CURSORB_PRECISION_16 (0<<31)
> #define DDL_CURSORB_SHIFT 24
> +#define DDL_SPRITED_PRECISION_32 (1<<23)
> +#define DDL_SPRITED_PRECISION_16 (0<<23)
> +#define DDL_SPRITED_SHIFT 16
> +#define DDL_SPRITEC_PRECISION_32 (1<<15)
> +#define DDL_SPRITEC_PRECISION_16 (0<<15)
> +#define DDL_SPRITEC_SHIFT 8
> #define DDL_PLANEB_PRECISION_32 (1<<7)
> #define DDL_PLANEB_PRECISION_16 (0<<7)
> +#define DDL_PLANEB_SHIFT 0
> +
> +#define VLV_DDL3 (VLV_DISPLAY_BASE + 0x70058)
> +#define DDL_CURSORC_PRECISION_32 (1<<31)
> +#define DDL_CURSORC_PRECISION_16 (0<<31)
> +#define DDL_CURSORC_SHIFT 24
> +#define DDL_SPRITEF_PRECISION_32 (1<<23)
> +#define DDL_SPRITEF_PRECISION_16 (0<<23)
> +#define DDL_SPRITEF_SHIFT 16
> +#define DDL_SPRITEE_PRECISION_32 (1<<15)
> +#define DDL_SPRITEE_PRECISION_16 (0<<15)
> +#define DDL_SPRITEE_SHIFT 8
> +#define DDL_PLANEC_PRECISION_32 (1<<7)
> +#define DDL_PLANEC_PRECISION_16 (0<<7)
> +#define DDL_PLANEC_SHIFT 0
>
> /* FIFO watermark sizes etc */
> #define G4X_FIFO_LINE_SIZE 64
> --
> 1.8.3.2
>
> _______________________________________________
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--
Jani Nikula, Intel Open Source Technology Center
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