On Wed, Aug 06, 2025 at 08:22:13AM +0300, Jouni Högander wrote: > We are currently observing crc failures after we started using dsb for PSR > updates as well. This seems to happen because PSR HW is still sending > couple of updates using old framebuffers on wake-up. > > Fix this by adding poll ensuring PSR is idle before starting update. > > Signed-off-by: Jouni Högander <jouni.hogan...@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index c1a3a95c65f0..411c74c73eae 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -7271,6 +7271,8 @@ static void intel_atomic_dsb_finish(struct > intel_atomic_state *state, > intel_psr_trigger_frame_change_event(new_crtc_state->dsb_commit, > state, crtc); > > + intel_psr_wait_for_idle_dsb(new_crtc_state); > + > if (new_crtc_state->use_dsb) > intel_dsb_vblank_evade(state, > new_crtc_state->dsb_commit);
How come the 'evade scanline 0 + normal evasion' in intel_dsb_vblank_evade() is not enough here? -- Ville Syrjälä Intel
