[PATCH 01/14] drm/i915: Drop the cached per-pipe min_cdclk[] from bw state

[Ville Syrjala]

From: Ville Syrjälä <ville.syrj...@linux.intel.com>

intel_bw_crtc_min_cdclk() only depends on the pipe data rate,
which we already have stashed in bw_state->data_rate[]. So
stashing the resulting min_cdclk[] as well is redundant. Get
rid of it.

Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 17 +++++++----------
 drivers/gpu/drm/i915/display/intel_bw.h |  1 -
 2 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c 
b/drivers/gpu/drm/i915/display/intel_bw.c
index 048be2872247..7b9ae926c5c4 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -795,15 +795,13 @@ static unsigned int intel_bw_crtc_data_rate(const struct 
intel_crtc_state *crtc_
 }
 
 /* "Maximum Pipe Read Bandwidth" */
-static int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
+static int intel_bw_crtc_min_cdclk(struct drm_i915_private *i915,
+                                  unsigned int data_rate)
 {
-       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-       struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-
        if (DISPLAY_VER(i915) < 12)
                return 0;
 
-       return 
DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
+       return DIV_ROUND_UP_ULL(mul_u32_u32(data_rate, 10), 512);
 }
 
 static unsigned int intel_bw_num_active_planes(struct drm_i915_private 
*dev_priv,
@@ -1138,7 +1136,8 @@ static bool intel_bw_state_changed(struct 
drm_i915_private *i915,
                                return true;
                }
 
-               if (old_bw_state->min_cdclk[pipe] != 
new_bw_state->min_cdclk[pipe])
+               if (intel_bw_crtc_min_cdclk(i915, 
old_bw_state->data_rate[pipe]) !=
+                   intel_bw_crtc_min_cdclk(i915, 
new_bw_state->data_rate[pipe]))
                        return true;
        }
 
@@ -1238,7 +1237,8 @@ int intel_bw_min_cdclk(struct drm_i915_private *i915,
        min_cdclk = intel_bw_dbuf_min_cdclk(i915, bw_state);
 
        for_each_pipe(i915, pipe)
-               min_cdclk = max(min_cdclk, bw_state->min_cdclk[pipe]);
+               min_cdclk = max(min_cdclk,
+                               intel_bw_crtc_min_cdclk(i915, 
bw_state->data_rate[pipe]));
 
        return min_cdclk;
 }
@@ -1266,9 +1266,6 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state 
*state,
                old_bw_state = intel_atomic_get_old_bw_state(state);
 
                skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);
-
-               new_bw_state->min_cdclk[crtc->pipe] =
-                       intel_bw_crtc_min_cdclk(crtc_state);
        }
 
        if (!old_bw_state)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h 
b/drivers/gpu/drm/i915/display/intel_bw.h
index 3313e4eac4f0..e977c3586dc3 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -55,7 +55,6 @@ struct intel_bw_state {
         */
        bool force_check_qgv;
 
-       int min_cdclk[I915_MAX_PIPES];
        unsigned int data_rate[I915_MAX_PIPES];
        u8 num_active_planes[I915_MAX_PIPES];
 };
-- 
2.45.3