On Mon, Feb 24, 2025 at 11:47:12AM +0530, Ankit Nautiyal wrote:
> For platforms for which vrr timing generator is always set, VRR_CTL
> enable bit does not need to toggle, so modify the vrr_{enable/disable}
> for this.
> At the moment the helper intel_vrr_always_use_vrr_tg() return false for
> all cases. This will be set later when all other bits are in place.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 40 ++++++++++++++++--------
> 1 file changed, 27 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 024c3014670a..11b7edbdb116 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -549,6 +549,16 @@ bool intel_vrr_is_push_sent(const struct
> intel_crtc_state *crtc_state)
> return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) &
> TRANS_PUSH_SEND;
> }
>
> +static
> +bool intel_vrr_always_use_vrr_tg(struct intel_display *display)
> +{
> + if (!HAS_VRR(display))
> + return false;
> +
> + /* #TODO return true for platforms supporting fixed_rr */
> + return false;
> +}
> +
> void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> @@ -570,13 +580,15 @@ void intel_vrr_enable(const struct intel_crtc_state
> *crtc_state)
> intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
> TRANS_PUSH_EN);
>
> - if (crtc_state->cmrr.enable) {
> - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> - VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
> - trans_vrr_ctl(crtc_state));
> - } else {
> - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
> + if (!intel_vrr_always_use_vrr_tg(display)) {
> + if (crtc_state->cmrr.enable) {
> + intel_de_write(display, TRANS_VRR_CTL(display,
> cpu_transcoder),
> + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE
> |
> + trans_vrr_ctl(crtc_state));
> + } else {
> + intel_de_write(display, TRANS_VRR_CTL(display,
> cpu_transcoder),
> + VRR_CTL_VRR_ENABLE |
> trans_vrr_ctl(crtc_state));
> + }
> }
> }
>
> @@ -591,12 +603,14 @@ void intel_vrr_disable(const struct intel_crtc_state
> *old_crtc_state)
> if (intel_crtc_is_joiner_secondary(old_crtc_state))
> return;
>
> - intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> - trans_vrr_ctl(old_crtc_state));
> - intel_de_wait_for_clear(display,
> - TRANS_VRR_STATUS(display, cpu_transcoder),
> - VRR_STATUS_VRR_EN_LIVE, 1000);
> - intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
> + if (!intel_vrr_always_use_vrr_tg(display)) {
> + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> + trans_vrr_ctl(old_crtc_state));
> + intel_de_wait_for_clear(display,
> + TRANS_VRR_STATUS(display,
> cpu_transcoder),
> + VRR_STATUS_VRR_EN_LIVE, 1000);
> + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0);
> + }
>
> intel_vrr_set_fixed_rr_timings(old_crtc_state);
> }
> --
> 2.45.2
--
Ville Syrjälä
Intel
