On Thu, Jan 30, 2025 at 01:51:53PM +0200, Jani Nikula wrote:
> On Wed, 29 Jan 2025, Imre Deak <imre.d...@intel.com> wrote:
> > From: Imre Deak <imre.d...@gmail.com>
> >
> > Fix the port width programming in the DDI_BUF_CTL register on MTLP+,
> > where this had an off-by-one error.
>
> Fixes: b66a8abaa48a ("drm/i915/display/mtl: Fill port width in
> DDI_BUF_/TRANS_DDI_FUNC_/PORT_BUF_CTL for HDMI")
> Cc: <sta...@vger.kernel.org> # v6.5+
I wasn't sure if this has any effect on the HW, since HDMI seemed to
work at least on MTLP regardless. Earlier platforms ignored the port
width in DDI_BUF_CTL for HDMI, maybe it's actually the same on new HW
as well. But it's better to do what the spec says.
> Reviewed-by: Jani Nikula <jani.nik...@intel.com>
>
> However, if this gets backported, it'll break DSI. Patch 1 needs to
> accompany it.
>
> Either add the same Fixes line to patch 1, or squash patches 1-2
> together.
Ok, will add the Fixes: line to patch 1 as well.
> > Signed-off-by: Imre Deak <imre.d...@gmail.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> > drivers/gpu/drm/i915/i915_reg.h | 2 +-
> > 2 files changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index dc319f37b1be9..36e7dde422d37 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3501,7 +3501,7 @@ static void intel_ddi_enable_hdmi(struct
> > intel_atomic_state *state,
> > intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port),
> > XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL,
> > port_buf);
> >
> > - buf_ctl |= DDI_PORT_WIDTH(lane_count);
> > + buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);
> >
> > if (DISPLAY_VER(dev_priv) >= 20)
> > buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 03da51b03fb90..04e47d0a8ab92 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3635,7 +3635,7 @@ enum skl_power_gate {
> > #define DDI_BUF_IS_IDLE (1 << 7)
> > #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
> > #define DDI_A_4_LANES (1 << 4)
> > -#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
> > +#define DDI_PORT_WIDTH(width) (((width) == 3 ? 4 :
> > ((width) - 1)) << 1)
> > #define DDI_PORT_WIDTH_MASK (7 << 1)
> > #define DDI_PORT_WIDTH_SHIFT 1
> > #define DDI_INIT_DISPLAY_DETECTED (1 << 0)
>
> --
> Jani Nikula, Intel
