On Fri, Mar 21, 2014 at 08:58:08PM +0530, sourab.gu...@intel.com wrote: > From: Akash Goel <akash.g...@intel.com> > > This patch Enables the bit for TLB invalidate in GFX Mode register. > > According to bspec, When enabled this bit limits the invalidation > of the TLB only to batch buffer boundaries, to pipe_control > commands which have the TLB invalidation bit set and sync flushes. > If disabled, the TLB caches are flushed for every full flush of > the pipeline. > > v2: Explicitly enabling TLB invalidate bit instead of assuming > default 1 (Chris Wilson)
Right, but there is nothing special about this code for vlv, all of gen7 share the same TLB invalidation code, and there is no documented reason not to do the switch. So do a cursory test on ivb/hsw and send a patch that doesn't say FIXME. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
