On 18.08.2022 16:41, Radhakrishna Sripada wrote: > From: Matt Roper <matthew.d.ro...@intel.com> > > Unlike the Xe_HP platforms, MTL only has a single CCS engine; the > quad-based engine masking logic does not apply to this platform (or > presumably any future platforms that only have 0 or 1 CCS). > > Signed-off-by: Matt Roper <matthew.d.ro...@intel.com> > Signed-off-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanan...@intel.com> > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > index 37fa813af766..17e7f20bbb48 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c > @@ -672,7 +672,7 @@ static void engine_mask_apply_compute_fuses(struct > intel_gt *gt) > unsigned long ccs_mask; > unsigned int i; > > - if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) > + if (hweight32(CCS_MASK(gt)) <= 1) > return; > > ccs_mask = > intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, > -- > 2.25.1 >
