On 18.08.2022 16:41, Radhakrishna Sripada wrote:
> From: Matt Roper <matthew.d.ro...@intel.com>
>
> Previously only dgfx platforms had a 4MB MMIO range, but starting with
> MTL we now use the larger range for all platforms.
>
> Bspec: 63834, 63830
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanan...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index a852c471d1b3..e0a8a8cb2052 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2232,14 +2232,15 @@ int intel_uncore_setup_mmio(struct intel_uncore
> *uncore, phys_addr_t phys_addr)
> * clobbering the GTT which we want ioremap_wc instead. Fortunately,
> * the register BAR remains the same size for all the earlier
> * generations up to Ironlake.
> - * For dgfx chips register range is expanded to 4MB.
> + * For dgfx chips register range is expanded to 4MB, and this larger
> + * range is also used for integrated gpus beginning with Meteor Lake.
> */
> - if (GRAPHICS_VER(i915) < 5)
> - mmio_size = 512 * 1024;
> - else if (IS_DGFX(i915))
> + if (IS_DGFX(i915) || GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> mmio_size = 4 * 1024 * 1024;
> - else
> + else if (GRAPHICS_VER(i915) >= 5)
> mmio_size = 2 * 1024 * 1024;
> + else
> + mmio_size = 512 * 1024;
>
> uncore->regs = ioremap(phys_addr, mmio_size);
> if (uncore->regs == NULL) {
> --
> 2.25.1
>
