Sometimes we might need to change the way we calculate
watermarks, based on which particular plane it is calculated
for. Thus it would be convenient to pass plane_id to those
functions.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2ff260117476..c5c1b6bef9a2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4274,6 +4274,7 @@ static int skl_compute_wm_params(const struct
intel_crtc_state *crtc_state,
u32 plane_pixel_rate, struct skl_wm_params *wp,
int color_plane);
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
+ enum plane_id plane_id,
int level,
unsigned int latency,
const struct skl_wm_params *wp,
@@ -4300,7 +4301,7 @@ skl_cursor_allocation(const struct intel_crtc_state
*crtc_state,
for (level = 0; level <= max_level; level++) {
unsigned int latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+ skl_compute_plane_wm(crtc_state, PLANE_CURSOR, level, latency,
&wp, &wm, &wm);
if (wm.min_ddb_alloc == U16_MAX)
break;
@@ -5530,6 +5531,7 @@ static int skl_wm_max_lines(struct drm_i915_private
*dev_priv)
}
static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
+ enum plane_id plane_id,
int level,
unsigned int latency,
const struct skl_wm_params *wp,
@@ -5657,6 +5659,7 @@ static void skl_compute_plane_wm(const struct
intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
+ enum plane_id plane_id,
const struct skl_wm_params *wm_params,
struct skl_wm_level *levels)
{
@@ -5668,7 +5671,7 @@ skl_compute_wm_levels(const struct intel_crtc_state
*crtc_state,
struct skl_wm_level *result = &levels[level];
unsigned int latency = dev_priv->wm.skl_latency[level];
- skl_compute_plane_wm(crtc_state, level, latency,
+ skl_compute_plane_wm(crtc_state, plane_id, level, latency,
wm_params, result_prev, result);
result_prev = result;
@@ -5676,6 +5679,7 @@ skl_compute_wm_levels(const struct intel_crtc_state
*crtc_state,
}
static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
+ enum plane_id plane_id,
const struct skl_wm_params *wm_params,
struct skl_plane_wm *plane_wm)
{
@@ -5684,7 +5688,7 @@ static void tgl_compute_sagv_wm(const struct
intel_crtc_state *crtc_state,
struct skl_wm_level *levels = plane_wm->wm;
unsigned int latency = dev_priv->wm.skl_latency[0] +
dev_priv->sagv_block_time_us;
- skl_compute_plane_wm(crtc_state, 0, latency,
+ skl_compute_plane_wm(crtc_state, plane_id, 0, latency,
wm_params, &levels[0],
sagv_wm);
}
@@ -5767,13 +5771,13 @@ static int skl_build_plane_wm_single(struct
intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, plane_id, &wm_params, wm->wm);
skl_compute_transition_wm(dev_priv, &wm->trans_wm,
&wm->wm[0], &wm_params);
if (DISPLAY_VER(dev_priv) >= 12) {
- tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
+ tgl_compute_sagv_wm(crtc_state, plane_id, &wm_params, wm);
skl_compute_transition_wm(dev_priv, &wm->sagv.trans_wm,
&wm->sagv.wm0, &wm_params);
@@ -5798,7 +5802,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state
*crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, plane_id, &wm_params, wm->uv_wm);
return 0;
}
--
2.24.1.485.gad05a3d8e5
