On Tue, Jul 13, 2021 at 08:14:58PM -0700, Matt Roper wrote:
> From: John Harrison <john.c.harri...@intel.com>
>
> Xe_HP can have a lot of extra media engines. This patch adds the reset
> support for them.
>
> Signed-off-by: John Harrison <john.c.harri...@intel.com>
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atw...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_reset.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 72251638d4ea..9586613ee399 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -515,8 +515,14 @@ static int gen11_reset_engines(struct intel_gt *gt,
> [VCS1] = GEN11_GRDOM_MEDIA2,
> [VCS2] = GEN11_GRDOM_MEDIA3,
> [VCS3] = GEN11_GRDOM_MEDIA4,
> + [VCS4] = GEN11_GRDOM_MEDIA5,
> + [VCS5] = GEN11_GRDOM_MEDIA6,
> + [VCS6] = GEN11_GRDOM_MEDIA7,
> + [VCS7] = GEN11_GRDOM_MEDIA8,
> [VECS0] = GEN11_GRDOM_VECS,
> [VECS1] = GEN11_GRDOM_VECS2,
> + [VECS2] = GEN11_GRDOM_VECS3,
> + [VECS3] = GEN11_GRDOM_VECS4,
> };
> struct intel_engine_cs *engine;
> intel_engine_mask_t tmp;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index af8f14fe4026..1eca88ac7057 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -395,10 +395,18 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN11_GRDOM_MEDIA2 (1 << 6)
> #define GEN11_GRDOM_MEDIA3 (1 << 7)
> #define GEN11_GRDOM_MEDIA4 (1 << 8)
> +#define GEN11_GRDOM_MEDIA5 (1 << 9)
> +#define GEN11_GRDOM_MEDIA6 (1 << 10)
> +#define GEN11_GRDOM_MEDIA7 (1 << 11)
> +#define GEN11_GRDOM_MEDIA8 (1 << 12)
> #define GEN11_GRDOM_VECS (1 << 13)
> #define GEN11_GRDOM_VECS2 (1 << 14)
> +#define GEN11_GRDOM_VECS3 (1 << 15)
> +#define GEN11_GRDOM_VECS4 (1 << 16)
> #define GEN11_GRDOM_SFC0 (1 << 17)
> #define GEN11_GRDOM_SFC1 (1 << 18)
> +#define GEN11_GRDOM_SFC2 (1 << 19)
> +#define GEN11_GRDOM_SFC3 (1 << 20)
>
> #define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 <<
> ((instance) >> 1))
> #define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance))
> --
> 2.25.4
>
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