On Tue, 2021-07-13 at 20:14 -0700, Matt Roper wrote:
> From: Lucas De Marchi <lucas.demar...@intel.com>
>
> Our _FEATURES macro went back to GEN7, extending each other, making it
> difficult to grasp what was really enabled/disabled. Take the
> opportunity of the GEN -> XE_HP name break and also break with the
> feature inheritance.
>
> For XE_HP this basically goes from GEN12 back to GEN7 coalescing the
> features making sure the overrides remain, remove all the
> display-specific features and sort it.
>
> Then also remove the definitions that would be overridden by
> DGFX_FEATURES and those that were 0 (since that is the default).
> Exception here is has_master_unit_irq: although it is a feature that
> started with DG1 and is true for all DGFX platforms, it's also true for
> XE_HP in general.
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
>
> Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 67696d752271..be5ee5e0e324 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -995,6 +995,30 @@ static const struct intel_device_info adl_p_info = {
> };
>
> #undef GEN
> +
> +#define XE_HP_PAGE_SIZES \
> + .page_sizes = I915_GTT_PAGE_SIZE_4K | \
> + I915_GTT_PAGE_SIZE_64K | \
> + I915_GTT_PAGE_SIZE_2M
> +
> +#define XE_HP_FEATURES \
> + .graphics_ver = 12, \
> + .graphics_rel = 50, \
> + XE_HP_PAGE_SIZES, \
> + .dma_mask_size = 46, \
> + .has_64bit_reloc = 1, \
> + .has_global_mocs = 1, \
> + .has_gt_uc = 1, \
> + .has_llc = 1, \
> + .has_logical_ring_contexts = 1, \
> + .has_logical_ring_elsq = 1, \
> + .has_rc6 = 1, \
> + .has_reset_engine = 1, \
> + .has_rps = 1, \
> + .has_runtime_pm = 1, \
> + .ppgtt_size = 48, \
> + .ppgtt_type = INTEL_PPGTT_FULL
> +
> #undef PLATFORM
>
> /*
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