On Tue, 2021-07-13 at 20:15 -0700, Matt Roper wrote:
> As with DG1, DG2 has an ICL-style south display interface provided on
> the same PCI device. Add a fake PCH to ensure DG2 takes the appropriate
> codepaths for south display handling.
>
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
> Bspec: 54871, 50062, 49961, 53673
> Cc: Lucas De Marchi <lucas.demar...@intel.com>
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swa...@intel.com>
> Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
> Reviewed-by: Lucas De Marchi <lucas.demar...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_pch.c | 3 +++
> drivers/gpu/drm/i915/intel_pch.h | 2 ++
> 3 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 61dceb2a17c1..e2171bd2820e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -207,7 +207,7 @@ static void intel_hpd_init_pins(struct drm_i915_private
> *dev_priv)
> (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
> return;
>
> - if (HAS_PCH_DG1(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
> hpd->pch_hpd = hpd_sde_dg1;
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> hpd->pch_hpd = hpd_icp;
> diff --git a/drivers/gpu/drm/i915/intel_pch.c
> b/drivers/gpu/drm/i915/intel_pch.c
> index 4e92ae19189e..cc44164e242b 100644
> --- a/drivers/gpu/drm/i915/intel_pch.c
> +++ b/drivers/gpu/drm/i915/intel_pch.c
> @@ -211,6 +211,9 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
> if (IS_DG1(dev_priv)) {
> dev_priv->pch_type = PCH_DG1;
> return;
> + } else if (IS_DG2(dev_priv)) {
> + dev_priv->pch_type = PCH_DG2;
> + return;
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_pch.h
> b/drivers/gpu/drm/i915/intel_pch.h
> index e2f3f30c6445..7c0d83d292dc 100644
> --- a/drivers/gpu/drm/i915/intel_pch.h
> +++ b/drivers/gpu/drm/i915/intel_pch.h
> @@ -30,6 +30,7 @@ enum intel_pch {
>
> /* Fake PCHs, functionality handled on the same PCI dev */
> PCH_DG1 = 1024,
> + PCH_DG2,
> };
>
> #define INTEL_PCH_DEVICE_ID_MASK 0xff80
> @@ -62,6 +63,7 @@ enum intel_pch {
>
> #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
> #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
> +#define HAS_PCH_DG2(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
> #define HAS_PCH_ADP(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
> #define HAS_PCH_DG1(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
> #define HAS_PCH_JSP(dev_priv)
> (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
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