On Tue, Oct 06, 2020 at 02:01:54AM +0300, Imre Deak wrote:
> Atm, if a full modeset is performed during the initial modeset the link
> training will happen with uninitialized max DP rate and lane count. Make
> sure the corresponding encoder state is initialized by adding an encoder
> hook called during driver init and system resume.
>
> A better alternative would be to store all states in the CRTC state and
> make this state available for the link re-training code. Also instead of
> the DPCD read in the hook there should be really a proper sink HW
> readout in place. Both of these require a bigger rework, so for now opting
> for this minimal fix to make at least full initial modesets work.
>
> The patch is based on
> https://patchwork.freedesktop.org/patch/101473/?series=10354&rev=3
>
> v2: (Ville)
> - s/sanitize_state/sync_state/
> - No point in calling the hook when CRTC is disabled, remove the call.
> - No point in calling the hook for MST, remove it.
>
> v3: Check only DPCD_REV to avoid clobbering intel_dp->dpcd. (Ville)
>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Signed-off-by: Imre Deak <imre.d...@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 ++++++
> drivers/gpu/drm/i915/display/intel_display.c | 2 ++
> .../drm/i915/display/intel_display_types.h | 7 +++++
> drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 2 ++
> 5 files changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4e54c55ec99f..6f7bd67732f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4564,6 +4564,13 @@ void intel_ddi_get_config(struct intel_encoder
> *encoder,
> intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
> }
>
> +static void intel_ddi_sync_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + if (intel_crtc_has_dp_encoder(crtc_state))
> + intel_dp_sync_state(encoder, crtc_state);
> +}
> +
> static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -5182,6 +5189,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv,
> enum port port)
> encoder->update_pipe = intel_ddi_update_pipe;
> encoder->get_hw_state = intel_ddi_get_hw_state;
> encoder->get_config = intel_ddi_get_config;
> + encoder->sync_state = intel_ddi_sync_state;
> encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
> encoder->suspend = intel_dp_encoder_suspend;
> encoder->get_power_domains = intel_ddi_get_power_domains;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 755b83d47f9c..907e1d155443 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -18723,6 +18723,8 @@ static void intel_modeset_readout_hw_state(struct
> drm_device *dev)
>
> encoder->base.crtc = &crtc->base;
> encoder->get_config(encoder, crtc_state);
> + if (encoder->sync_state)
> + encoder->sync_state(encoder, crtc_state);
> } else {
> encoder->base.crtc = NULL;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5297b2f08ff9..65ae2070576f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -188,6 +188,13 @@ struct intel_encoder {
> void (*get_config)(struct intel_encoder *,
> struct intel_crtc_state *pipe_config);
>
> + /*
> + * Optional hook called during init/resume to sync any state
> + * stored in the encoder (eg. DP link parameters) wrt. the HW state.
> + */
> + void (*sync_state)(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
> +
> /*
> * Optional hook, returning true if this encoder allows a fastset
> * during the initial commit, false otherwise.
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index df5277c2b9ba..239016dcd544 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3703,6 +3703,33 @@ static void intel_dp_get_config(struct intel_encoder
> *encoder,
> }
> }
>
> +static bool
> +intel_dp_get_dpcd(struct intel_dp *intel_dp);
> +
> +/**
> + * intel_dp_sync_state - sync the encoder state during init/resume
> + * @encoder: intel encoder to sync
> + * @crtc_state: state for the CRTC connected to the encoder
> + *
> + * Sync any state stored in the encoder wrt. HW state during driver init
> + * and system resume.
> + */
> +void intel_dp_sync_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + /*
> + * Don't clobber DPCD if it's been already read out during output
> + * setup (eDP) or detect.
> + */
> + if (intel_dp->dpcd[DP_DPCD_REV] == 0)
> + intel_dp_get_dpcd(intel_dp);
> +
> + intel_dp->max_link_lane_count =
> intel_dp_max_common_lane_count(intel_dp);
> + intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
> +}
> +
> bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> @@ -8090,6 +8117,7 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
> intel_encoder->compute_config = intel_dp_compute_config;
> intel_encoder->get_hw_state = intel_dp_get_hw_state;
> intel_encoder->get_config = intel_dp_get_config;
> + intel_encoder->sync_state = intel_dp_sync_state;
> intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
> intel_encoder->update_pipe = intel_panel_update_backlight;
> intel_encoder->suspend = intel_dp_encoder_suspend;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 977585aea3c8..6c201377fdc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -143,5 +143,7 @@ int intel_dp_init_hdcp(struct intel_digital_port
> *dig_port,
>
> bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state);
> +void intel_dp_sync_state(struct intel_encoder *encoder,
> + const struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_DP_H__ */
> --
> 2.25.1
--
Ville Syrjälä
Intel
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