General purpose registers are per engine and
in a fixed location. Add to live_lrc_fixed.
Signed-off-by: Mika Kuoppala <mika.kuopp...@linux.intel.com>
Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 12 ++++++++++++
drivers/gpu/drm/i915/gt/selftest_lrc.c | 5 +++++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 214ea2a34693..c1f30fe12d5d 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -250,6 +250,18 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs
*engine)
return -1;
}
+static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
+{
+ if (INTEL_GEN(engine->i915) >= 12)
+ return 0x74;
+ else if (INTEL_GEN(engine->i915) >= 9)
+ return 0x68;
+ else if (engine->class == RENDER_CLASS)
+ return 0xd8;
+ else
+ return -1;
+}
+
static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)
{
if (INTEL_GEN(engine->i915) >= 12)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index e964c1402d29..d10c38aec500 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -4613,6 +4613,11 @@ static int live_lrc_fixed(void *arg)
CTX_TIMESTAMP - 1,
"RING_CTX_TIMESTAMP"
},
+ {
+
i915_mmio_reg_offset(GEN8_RING_CS_GPR(engine->mmio_base, 0)),
+ lrc_ring_gpr0(engine),
+ "RING_CS_GPR0"
+ },
{ },
}, *t;
u32 *hw;
--
2.17.1
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