General purpose registers are per engine and
in a fixed location. Add to live_lrc_fixed.
Signed-off-by: Mika Kuoppala <mika.kuopp...@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc_reg.h | 1 +
drivers/gpu/drm/i915/gt/selftest_lrc.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
index 93cb6c460508..008aa53e24a1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc_reg.h
@@ -26,6 +26,7 @@
#define CTX_PDP0_UDW (0x30 + 1)
#define CTX_PDP0_LDW (0x32 + 1)
#define CTX_R_PWR_CLK_STATE (0x42 + 1)
+#define CTX_CS_GPR_0 (0x74 + 1)
#define GEN9_CTX_RING_MI_MODE 0x54
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index e964c1402d29..4996d511f6fc 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -4613,6 +4613,11 @@ static int live_lrc_fixed(void *arg)
CTX_TIMESTAMP - 1,
"RING_CTX_TIMESTAMP"
},
+ {
+
i915_mmio_reg_offset(GEN8_RING_CS_GPR(engine->mmio_base, 0)),
+ CTX_CS_GPR_0 - 1,
+ "RING_CS_GPR_0"
+ },
{ },
}, *t;
u32 *hw;
--
2.17.1
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