On Tue, May 28, 2013 at 02:30:56PM +0100, Damien Lespiau wrote: > On Sat, Apr 27, 2013 at 05:59:20PM -0700, Ben Widawsky wrote: > > @@ -2720,12 +2720,12 @@ static void gen6_enable_rps(struct drm_device *dev) > > gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8); > > > > /* requires MSI enabled */ > > - I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); > > + I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS); > > spin_lock_irq(&dev_priv->rps.lock); > > WARN_ON(dev_priv->rps.pm_iir != 0); > > - I915_WRITE(GEN6_PMIMR, 0); > > + I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS); > > You're not unmasking the RPS interrupts in PMIMR here now. I'm missing > how they are enabled now.
You are right. It's fixed in a later patch IFF we have VEBOX, but would regress on IVB and HSW. Both this patch, and that are easily fixed. BRB. > > > spin_unlock_irq(&dev_priv->rps.lock); - /* enable all PM > > interrupts */ + /* unmask all PM interrupts */ > > I915_WRITE(GEN6_PMINTRMSK, 0); > > > > rc6vids = 0; -- Ben Widawsky, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
