On Sat, Apr 27, 2013 at 05:59:25PM -0700, Ben Widawsky wrote:
> v2: Use the correct lock to protect PM interrupt regs, this was
> accidentally lost from earlier (Haihao)
> Fix return types (Ben)
>
> CC: Xiang, Haihao <haihao.xi...@intel.com>
> Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
> ---
Reviewed-by: Damien Lespiau <damien.lesp...@intel.com>
--
Damien
> drivers/gpu/drm/i915/intel_ringbuffer.c | 46
> +++++++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/intel_ringbuffer.h | 5 ++--
> 2 files changed, 47 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index ccfa1f9..93a3128 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1005,6 +1005,48 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
> gen6_gt_force_wake_put(dev_priv);
> }
>
> +static bool
> +hsw_vebox_get_irq(struct intel_ring_buffer *ring)
> +{
> + struct drm_device *dev = ring->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned long flags;
> +
> + if (!dev->irq_enabled)
> + return false;
> +
> + spin_lock_irqsave(&dev_priv->rps.lock, flags);
> + if (ring->irq_refcount.pm++ == 0) {
> + u32 pm_imr = I915_READ(GEN6_PMIMR);
> + I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
> + I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
> + POSTING_READ(GEN6_PMIMR);
> + }
> + spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
> +
> + return true;
> +}
> +
> +static void
> +hsw_vebox_put_irq(struct intel_ring_buffer *ring)
> +{
> + struct drm_device *dev = ring->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned long flags;
> +
> + if (!dev->irq_enabled)
> + return;
> +
> + spin_lock_irqsave(&dev_priv->rps.lock, flags);
> + if (--ring->irq_refcount.pm == 0) {
> + u32 pm_imr = I915_READ(GEN6_PMIMR);
> + I915_WRITE_IMR(ring, ~0);
> + I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
> + POSTING_READ(GEN6_PMIMR);
> + }
> + spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
> +}
> +
> static int
> i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
> u32 offset, u32 length,
> @@ -1913,8 +1955,8 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
> ring->get_seqno = gen6_ring_get_seqno;
> ring->set_seqno = ring_set_seqno;
> ring->irq_enable_mask = 0;
> - ring->irq_get = NULL;
> - ring->irq_put = NULL;
> + ring->irq_get = hsw_vebox_get_irq;
> + ring->irq_put = hsw_vebox_put_irq;
> ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> ring->sync_to = gen6_ring_sync;
> ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
> b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 24b4413..d040dae 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -69,8 +69,9 @@ struct intel_ring_buffer {
> u32 last_retired_head;
>
> struct {
> - u32 gt;
> - } irq_refcount; /* protected by dev_priv->irq_lock */
> + u32 gt; /* protected by dev_priv->irq_lock */
> + u32 pm; /* protected by dev_priv->rps.lock (sucks) */
> + } irq_refcount;
> u32 irq_enable_mask; /* bitmask to enable ring
> interrupt */
> u32 trace_irq_seqno;
> u32 sync_seqno[I915_NUM_RINGS-1];
> --
> 1.8.2.1
>
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