On Thu, Aug 29, 2019 at 02:25:51AM -0700, Lucas De Marchi wrote:
> Gen 12 onwards moves the DP_TP_* registers to be transcoder-based rather
> than port-based. This adds the new register addresses and changes all
> the callers to use the register saved in intel_dp->regs.*. This is
> filled out when preparing to enable the port so we take into account if
> we should use the transcoder or the port.
>
> v2: reimplement by stashing the registers we want to access under
> intel_dp->reg. Now they are initialized when enabling the port.
> Ville suggested to store the transcoder to be used exclusively
> by TGL+. After implementing I thought just storing the register directly
> made it cleaner.
>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
Should we replace the direct usages of DP_TP_CTL DP_TP_STATUS in
hsw_fdi_link_train with as well for consistency? That code is specific
to HSW/BDW so it doesn't cause a problem, but there's always the risk
that it might get copy/pasted somewhere else where the direct register
usage is wrong.
Otherwise,
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
Matt
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++++++++++++-------
> .../drm/i915/display/intel_display_types.h | 9 ++++
> drivers/gpu/drm/i915/display/intel_dp.c | 13 +++---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++--
> drivers/gpu/drm/i915/i915_reg.h | 4 ++
> 5 files changed, 51 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index df3e4fe7e3e9..73f7a4b0f6c2 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3164,17 +3164,18 @@ static void intel_ddi_enable_fec(struct intel_encoder
> *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = encoder->port;
> + struct intel_dp *intel_dp;
> u32 val;
>
> if (!crtc_state->fec_enable)
> return;
>
> - val = I915_READ(DP_TP_CTL(port));
> + intel_dp = enc_to_intel_dp(&encoder->base);
> + val = I915_READ(intel_dp->regs.dp_tp_ctl);
> val |= DP_TP_CTL_FEC_ENABLE;
> - I915_WRITE(DP_TP_CTL(port), val);
> + I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
>
> - if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
> + if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
> DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
> DRM_ERROR("Timed out waiting for FEC Enable Status\n");
> }
> @@ -3183,16 +3184,17 @@ static void intel_ddi_disable_fec_state(struct
> intel_encoder *encoder,
> const struct intel_crtc_state
> *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = encoder->port;
> + struct intel_dp *intel_dp;
> u32 val;
>
> if (!crtc_state->fec_enable)
> return;
>
> - val = I915_READ(DP_TP_CTL(port));
> + intel_dp = enc_to_intel_dp(&encoder->base);
> + val = I915_READ(intel_dp->regs.dp_tp_ctl);
> val &= ~DP_TP_CTL_FEC_ENABLE;
> - I915_WRITE(DP_TP_CTL(port), val);
> - POSTING_READ(DP_TP_CTL(port));
> + I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
> + POSTING_READ(intel_dp->regs.dp_tp_ctl);
> }
>
> static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
> @@ -3205,10 +3207,14 @@ static void tgl_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
> int level = intel_ddi_dp_level(intel_dp);
> + enum transcoder transcoder = crtc_state->cpu_transcoder;
>
> intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> crtc_state->lane_count, is_mst);
>
> + intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
> + intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
> +
> /* 1.a got on intel_atomic_commit_tail() */
>
> /* 2. */
> @@ -3297,6 +3303,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder
> *encoder,
> intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
> crtc_state->lane_count, is_mst);
>
> + intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
> + intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
> +
> intel_edp_panel_on(intel_dp);
>
> intel_ddi_clk_select(encoder, crtc_state);
> @@ -3463,10 +3472,12 @@ static void intel_disable_ddi_buf(struct
> intel_encoder *encoder,
> }
>
> if (intel_encoder_is_dp(encoder)) {
> - val = I915_READ(DP_TP_CTL(port));
> + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> +
> + val = I915_READ(intel_dp->regs.dp_tp_ctl);
> val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> - I915_WRITE(DP_TP_CTL(port), val);
> + I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
> }
>
> /* Disable FEC in DP Sink */
> @@ -3895,7 +3906,7 @@ static void intel_ddi_prepare_link_retrain(struct
> intel_dp *intel_dp)
> u32 val;
> bool wait = false;
>
> - if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
> + if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) {
> val = I915_READ(DDI_BUF_CTL(port));
> if (val & DDI_BUF_CTL_ENABLE) {
> val &= ~DDI_BUF_CTL_ENABLE;
> @@ -3903,11 +3914,11 @@ static void intel_ddi_prepare_link_retrain(struct
> intel_dp *intel_dp)
> wait = true;
> }
>
> - val = I915_READ(DP_TP_CTL(port));
> + val = I915_READ(intel_dp->regs.dp_tp_ctl);
> val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> - I915_WRITE(DP_TP_CTL(port), val);
> - POSTING_READ(DP_TP_CTL(port));
> + I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
> + POSTING_READ(intel_dp->regs.dp_tp_ctl);
>
> if (wait)
> intel_wait_ddi_buf_idle(dev_priv, port);
> @@ -3922,8 +3933,8 @@ static void intel_ddi_prepare_link_retrain(struct
> intel_dp *intel_dp)
> if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
> }
> - I915_WRITE(DP_TP_CTL(port), val);
> - POSTING_READ(DP_TP_CTL(port));
> + I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
> + POSTING_READ(intel_dp->regs.dp_tp_ctl);
>
> intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 96514dcc7812..3745553ac3ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1211,6 +1211,15 @@ struct intel_dp {
> bool can_mst; /* this port supports mst */
> bool is_mst;
> int active_mst_links;
> +
> + /*
> + * DP_TP_* registers may be either on port or transcoder register space.
> + */
> + struct {
> + i915_reg_t dp_tp_ctl;
> + i915_reg_t dp_tp_status;
> + } regs;
> +
> /* connector directly attached - won't be use for modeset in mst world
> */
> struct intel_connector *attached_connector;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 00c3752fa197..938e6e7cccf1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2288,6 +2288,9 @@ static void intel_dp_prepare(struct intel_encoder
> *encoder,
> intel_crtc_has_type(pipe_config,
> INTEL_OUTPUT_DP_MST));
>
> + intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
> + intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
> +
> /*
> * There are four kinds of DP registers:
> *
> @@ -3237,7 +3240,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> dp_train_pat & train_pat_mask);
>
> if (HAS_DDI(dev_priv)) {
> - u32 temp = I915_READ(DP_TP_CTL(port));
> + u32 temp = I915_READ(intel_dp->regs.dp_tp_ctl);
>
> if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
> temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
> @@ -3263,7 +3266,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
> temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
> break;
> }
> - I915_WRITE(DP_TP_CTL(port), temp);
> + I915_WRITE(intel_dp->regs.dp_tp_ctl, temp);
>
> } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
> (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
> @@ -3961,10 +3964,10 @@ void intel_dp_set_idle_link_train(struct intel_dp
> *intel_dp)
> if (!HAS_DDI(dev_priv))
> return;
>
> - val = I915_READ(DP_TP_CTL(port));
> + val = I915_READ(intel_dp->regs.dp_tp_ctl);
> val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> val |= DP_TP_CTL_LINK_TRAIN_IDLE;
> - I915_WRITE(DP_TP_CTL(port), val);
> + I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
>
> /*
> * Until TGL on PORT_A we can have only eDP in SST mode. There the only
> @@ -3976,7 +3979,7 @@ void intel_dp_set_idle_link_train(struct intel_dp
> *intel_dp)
> if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
> return;
>
> - if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
> + if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
> DP_TP_STATUS_IDLE_DONE, 1))
> DRM_ERROR("Timed out waiting for DP idle patterns\n");
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 2c5ac3dd647f..2774126ca9ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -287,7 +287,6 @@ static void intel_mst_pre_enable_dp(struct intel_encoder
> *encoder,
> struct intel_digital_port *intel_dig_port = intel_mst->primary;
> struct intel_dp *intel_dp = &intel_dig_port->dp;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = intel_dig_port->base.port;
> struct intel_connector *connector =
> to_intel_connector(conn_state->connector);
> int ret;
> @@ -318,8 +317,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder
> *encoder,
> DRM_ERROR("failed to allocate vcpi\n");
>
> intel_dp->active_mst_links++;
> - temp = I915_READ(DP_TP_STATUS(port));
> - I915_WRITE(DP_TP_STATUS(port), temp);
> + temp = I915_READ(intel_dp->regs.dp_tp_status);
> + I915_WRITE(intel_dp->regs.dp_tp_status, temp);
>
> ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
>
> @@ -334,11 +333,10 @@ static void intel_mst_enable_dp(struct intel_encoder
> *encoder,
> struct intel_digital_port *intel_dig_port = intel_mst->primary;
> struct intel_dp *intel_dp = &intel_dig_port->dp;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = intel_dig_port->base.port;
>
> DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
>
> - if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
> + if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
> DP_TP_STATUS_ACT_SENT, 1))
> DRM_ERROR("Timed out waiting for ACT sent\n");
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 33d9d141ee8f..1c8fab11ed9d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9451,7 +9451,9 @@ enum skl_power_gate {
> /* DisplayPort Transport Control */
> #define _DP_TP_CTL_A 0x64040
> #define _DP_TP_CTL_B 0x64140
> +#define _TGL_DP_TP_CTL_A 0x60540
> #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
> +#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
> #define DP_TP_CTL_ENABLE (1 << 31)
> #define DP_TP_CTL_FEC_ENABLE (1 << 30)
> #define DP_TP_CTL_MODE_SST (0 << 27)
> @@ -9471,7 +9473,9 @@ enum skl_power_gate {
> /* DisplayPort Transport Status */
> #define _DP_TP_STATUS_A 0x64044
> #define _DP_TP_STATUS_B 0x64144
> +#define _TGL_DP_TP_STATUS_A 0x60544
> #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
> +#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
> #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
> #define DP_TP_STATUS_IDLE_DONE (1 << 25)
> #define DP_TP_STATUS_ACT_SENT (1 << 24)
> --
> 2.23.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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