Let's continue the migration starting from newer to old platforms.
The goal is to use intel_irq struct and intel_uncore_* functions
along all i915_irq.c as much as possible.
Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 36 ++++++++++++++++++---------------
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f142fe23bf10..cdb079459d29 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3100,9 +3100,9 @@ gen11_gt_irq_handler(struct intel_irq * const irq,
}
static u32
-gen11_gu_misc_irq_ack(struct drm_i915_private *dev_priv, const u32 master_ctl)
+gen11_gu_misc_irq_ack(struct intel_irq *irq, const u32 master_ctl)
{
- void __iomem * const regs = dev_priv->uncore.regs;
+ void __iomem * const regs = irq->uncore->regs;
u32 iir;
if (!(master_ctl & GEN11_GU_MISC_IRQ))
@@ -3172,7 +3172,7 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
enable_rpm_wakeref_asserts(i915);
}
- gu_misc_iir = gen11_gu_misc_irq_ack(i915, master_ctl);
+ gu_misc_iir = gen11_gu_misc_irq_ack(&i915->irq, master_ctl);
gen11_master_intr_enable(regs);
@@ -4175,31 +4175,35 @@ static int gen8_irq_postinstall(struct drm_device *dev)
return 0;
}
-static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
+static void gen11_gt_irq_postinstall(struct intel_irq *irq)
{
+ struct intel_uncore *uncore = irq->uncore;
const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
BUILD_BUG_ON(irqs & 0xffff0000);
/* Enable RCS, BCS, VCS and VECS class interrupts. */
- I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
- I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 | irqs);
+ intel_uncore_write(uncore, GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 |
irqs);
+ intel_uncore_write(uncore, GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 |
irqs);
/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
- I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16));
- I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16));
- I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs << 16));
- I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16));
- I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16));
+ intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16));
+ intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16));
+ intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK,
+ ~(irqs | irqs << 16));
+ intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK,
+ ~(irqs | irqs << 16));
+ intel_uncore_write(uncore, GEN11_VECS0_VECS1_INTR_MASK,
+ ~(irqs | irqs << 16));
/*
* RPS interrupts will get enabled/disabled on demand when RPS itself
* is enabled/disabled.
*/
- dev_priv->irq.pm_ier = 0x0;
- dev_priv->irq.pm_imr = ~dev_priv->irq.pm_ier;
- I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
- I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
+ irq->pm_ier = 0x0;
+ irq->pm_imr = ~irq->pm_ier;
+ intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
+ intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
}
static void icp_irq_postinstall(struct drm_device *dev)
@@ -4226,7 +4230,7 @@ static int gen11_irq_postinstall(struct drm_device *dev)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
icp_irq_postinstall(dev);
- gen11_gt_irq_postinstall(dev_priv);
+ gen11_gt_irq_postinstall(irq);
gen8_de_irq_postinstall(dev_priv);
GEN3_IRQ_INIT(irq, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
--
2.20.1
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