On Wed, Oct 03, 2018 at 12:52:03PM +0530, Mahesh Kumar wrote:
> DDI/TC clock-off bits are not equally distanced. TC1-3 bits are
> from offset 12 & TC4 is at offset 21.
> Create a function to choose correct clk-off bit.
>
> Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulka...@intel.com>
> Cc: Lucas De Marchi <lucas.demar...@intel.com>
Missing Fixes tag.
Lucas De Marchi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++++++---
> 2 files changed, 21 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eaf3e0d529d3..e1a2851a28cf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9302,6 +9302,9 @@ enum skl_power_gate {
> #define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
> #define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_F ? 23 :
> \
> (port) + 10))
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
> +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4
> ? \
> + 21 : (tc_port) + 12))
> #define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) == PORT_F ? 21
> : \
> (port) * 2)
> #define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 <<
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index b5b8dae06cde..9883f02756ab 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2733,6 +2733,21 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> return DDI_BUF_TRANS_SELECT(level);
> }
>
> +static inline
> +uint32_t icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> + enum port port)
> +{
> + if (intel_port_is_combophy(dev_priv, port)) {
> + return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + } else if (intel_port_is_tc(dev_priv, port)) {
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> +
> + return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
> + }
> +
> + return 0;
> +}
> +
> void icl_map_plls_to_ports(struct drm_crtc *crtc,
> struct intel_crtc_state *crtc_state,
> struct drm_atomic_state *old_state)
> @@ -2756,7 +2771,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
> mutex_lock(&dev_priv->dpll_lock);
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> - WARN_ON((val & DPCLKA_CFGCR0_DDI_CLK_OFF(port)) == 0);
> + WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
>
> if (intel_port_is_combophy(dev_priv, port)) {
> val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> @@ -2765,7 +2780,7 @@ void icl_map_plls_to_ports(struct drm_crtc *crtc,
> POSTING_READ(DPCLKA_CFGCR0_ICL);
> }
>
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> mutex_unlock(&dev_priv->dpll_lock);
> @@ -2793,7 +2808,7 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
> mutex_lock(&dev_priv->dpll_lock);
> I915_WRITE(DPCLKA_CFGCR0_ICL,
> I915_READ(DPCLKA_CFGCR0_ICL) |
> - DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> + icl_dpclka_cfgcr0_clk_off(dev_priv, port));
> mutex_unlock(&dev_priv->dpll_lock);
> }
> }
> --
> 2.16.2
>
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