On Wed, Oct 31, 2012 at 06:12:35PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zan...@intel.com>
>
> From the mode set sequence document: "Each setting should be tried at
> least twice before failing mode set".
>
> Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index f8ca3c4..94c6b76 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -179,7 +179,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
> I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
>
> /* Start the training iterating through available voltages and emphasis
> */
> - for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {
> + for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) {
> /* Configure DP_TP_CTL with auto-training */
> I915_WRITE(DP_TP_CTL(PORT_E),
> DP_TP_CTL_FDI_AUTOTRAIN |
> @@ -191,7 +191,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
> I915_WRITE(DDI_BUF_CTL(PORT_E),
> DDI_BUF_CTL_ENABLE |
> ((intel_crtc->fdi_lanes - 1) << 1) |
> - hsw_ddi_buf_ctl_values[i]);
> + hsw_ddi_buf_ctl_values[i >> 1]);
I think a simple / 2 is clearer here and symmetric with the * 2 above. The
compiler will apply clever tricks for you anyway ;-)
-Daniel
> POSTING_READ(DDI_BUF_CTL(PORT_E));
>
> udelay(600);
> --
> 1.7.11.4
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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